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1. PIPELINED_ADDER PIPELINED_ADDER Public

   8-input pipelined adder tree in Verilog with simulation & synthesis results.

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2. FIR_FILTER_PROJECT FIR_FILTER_PROJECT Public

   64-Tap FIR Filter using Verilog with testbench, simulation results, and Q1.15 coefficient implementation.

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3. DUAL_PORT_RAM DUAL_PORT_RAM Public

   This repository contains a complete Dual Port RAM Design in Verilog, developed as part of my hardware design learning journey. The project is divided into 4 structured phases, each focusing on a sp…

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4. Verilog Verilog Public

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