Odb hierarchical

[oharboe]

OPENROAD_HIERARCHICAL=1

@maliberty @jhkim-pii FYI

[oharboe]

Looks like it worked... Very readable:

>>> report_checks -from {core/REG$_DFF_P_/QN} -to {core/int_issue_unit/io_dis_uops_0_ready_REG$_DFF_P_/D}
Startpoint: core/REG$_DFF_P_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: core/int_issue_unit/io_dis_uops_0_ready_REG$_DFF_P_
          (rising edge-triggered flip-flop clocked by clock)
Path Group: reg2reg
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ core/REG$_DFF_P_/CLK (DFFHQNx1_ASAP7_75t_R)
  41.92   41.92 v core/REG$_DFF_P_/QN (DFFHQNx1_ASAP7_75t_R)
  26.67   68.59 ^ core/_34434_/Y (INVx1_ASAP7_75t_R)
 371.84  440.42 ^ core/_34435_/Y (BUFx2_ASAP7_75t_R)
  76.76  517.18 ^ lsu/_707799_/Y (BUFx2_ASAP7_75t_R)
  29.58  546.76 ^ dcache/_15601_/Y (BUFx2_ASAP7_75t_R)
   9.17  555.93 v dcache/_15648_/Y (NAND2x1_ASAP7_75t_R)
  20.87  576.80 v dcache/_15649_/Y (AND4x1_ASAP7_75t_R)
  18.52  595.33 v dcache/_19771_/Y (AND3x1_ASAP7_75t_R)
  21.39  616.72 v dcache/mshrs/_08315_/Y (BUFx2_ASAP7_75t_R)
  25.15  641.87 ^ dcache/mshrs/_08316_/Y (INVx1_ASAP7_75t_R)
  14.33  656.19 v dcache/mshrs/_09583_/Y (AOI21x1_ASAP7_75t_R)
 192.53  848.73 ^ dcache/mshrs/_09584_/Y (INVx1_ASAP7_75t_R)
  42.72  891.44 ^ dcache/mshrs/mshrs_2/_1104_/Y (OR3x1_ASAP7_75t_R)
  11.69  903.13 v dcache/mshrs/mshrs_2/_1105_/Y (OAI21x1_ASAP7_75t_R)
  23.20  926.33 ^ dcache/mshrs/mshrs_2/_1106_/Y (AOI22x1_ASAP7_75t_R)
  31.39  957.72 ^ dcache/mshrs/mshrs_2/_1120_/Y (OA21x2_ASAP7_75t_R)
  20.62  978.34 ^ dcache/mshrs/_09748_/Y (AND3x1_ASAP7_75t_R)
  24.80 1003.14 ^ dcache/mshrs/_09749_/Y (AND4x1_ASAP7_75t_R)
  17.72 1020.86 ^ dcache/mshrs/_09750_/Y (AO32x1_ASAP7_75t_R)
  19.37 1040.23 ^ dcache/mshrs/_09751_/Y (OR5x1_ASAP7_75t_R)
  20.39 1060.63 ^ dcache/mshrs/_09752_/Y (OA21x2_ASAP7_75t_R)
   8.70 1069.33 v dcache/mshrs/_09753_/Y (NAND2x2_ASAP7_75t_R)
  16.03 1085.36 v dcache/mshrs/_16018_/Y (AO21x1_ASAP7_75t_R)
  10.92 1096.28 ^ dcache/mshrs/_16019_/Y (AOI21x1_ASAP7_75t_R)
  21.34 1117.62 ^ dcache/_15611_/Y (AND3x1_ASAP7_75t_R)
  25.35 1142.97 ^ dcache/_15612_/Y (AND4x1_ASAP7_75t_R)
  20.31 1163.29 ^ dcache/_15613_/Y (AND3x1_ASAP7_75t_R)
  20.96 1184.24 ^ dcache/_15614_/Y (OR3x1_ASAP7_75t_R)
  22.49 1206.74 ^ dcache/_15620_/Y (AND3x1_ASAP7_75t_R)
  19.50 1226.24 ^ dcache/_15621_/Y (BUFx2_ASAP7_75t_R)
  23.40 1249.64 ^ dcache/_15622_/Y (BUFx2_ASAP7_75t_R)
  24.02 1273.67 ^ dcache/_22208_/Y (BUFx2_ASAP7_75t_R)
  22.36 1296.03 ^ dcache/_23754_/Y (AND3x1_ASAP7_75t_R)
  14.49 1310.52 ^ dcache/_23755_/Y (AO21x1_ASAP7_75t_R)
  23.39 1333.91 ^ lsu/_408944_/Y (BUFx2_ASAP7_75t_R)
  12.97 1346.88 v lsu/_408970_/Y (INVx1_ASAP7_75t_R)
  26.80 1373.68 ^ lsu/_408974_/Y (NAND2x1_ASAP7_75t_R)
  26.24 1399.92 ^ lsu/_408987_/Y (OR2x2_ASAP7_75t_R)
  23.74 1423.66 ^ lsu/_408988_/Y (BUFx2_ASAP7_75t_R)
  10.99 1434.64 v lsu/_661956_/Y (OAI22x1_ASAP7_75t_R)
  26.81 1461.46 v lsu/_661960_/Y (OR4x1_ASAP7_75t_R)
  38.35 1499.80 v lsu/_661961_/Y (OR5x1_ASAP7_75t_R)
  30.58 1530.38 v lsu/_661962_/Y (OR4x1_ASAP7_75t_R)
  25.59 1555.97 v lsu/_661963_/Y (OA211x2_ASAP7_75t_R)
   5.58 1561.56 ^ lsu/_661964_/Y (INVx1_ASAP7_75t_R)
  18.55 1580.11 ^ lsu/_661965_/Y (OA211x2_ASAP7_75t_R)
  12.05 1592.15 ^ lsu/_661966_/Y (AO21x1_ASAP7_75t_R)
  27.90 1620.06 v lsu/_661967_/Y (XNOR2x2_ASAP7_75t_R)
  18.28 1638.34 v lsu/_662107_/Y (AND5x1_ASAP7_75t_R)
  15.73 1654.07 v lsu/_662108_/Y (AO21x1_ASAP7_75t_R)
 628.36 2282.42 ^ lsu/_662447_/Y (AOI21x1_ASAP7_75t_R)
  73.55 2355.98 v core/int_issue_unit/slots_32/_2309_/Y (OAI21x1_ASAP7_75t_R)
  42.12 2398.10 ^ core/int_issue_unit/slots_32/_2310_/Y (NAND2x1_ASAP7_75t_R)
  16.49 2414.59 v core/int_issue_unit/slots_32/_2161_/Y (NAND2x1_ASAP7_75t_R)
  23.22 2437.81 ^ core/int_issue_unit/slots_32/_2210_/Y (NAND2x1_ASAP7_75t_R)
  21.55 2459.36 ^ core/int_issue_unit/_123530_/Y (AO22x1_ASAP7_75t_R)
  13.14 2472.50 ^ core/int_issue_unit/_123532_/Y (AO21x1_ASAP7_75t_R)
  19.72 2492.22 ^ core/int_issue_unit/_123533_/Y (AND3x1_ASAP7_75t_R)
  11.64 2503.86 ^ core/int_issue_unit/_123534_/Y (AO21x1_ASAP7_75t_R)
  34.16 2538.02 ^ core/int_issue_unit/_123539_/Y (AO21x1_ASAP7_75t_R)
  29.91 2567.94 ^ core/int_issue_unit/_213450_/Y (OR2x2_ASAP7_75t_R)
  54.34 2622.27 v core/int_issue_unit/_243806_/SN (FAx1_ASAP7_75t_R)
  28.04 2650.31 ^ core/int_issue_unit/_243807_/CON (FAx1_ASAP7_75t_R)
  14.80 2665.10 v core/int_issue_unit/_243807_/SN (FAx1_ASAP7_75t_R)
  13.25 2678.35 ^ core/int_issue_unit/_213468_/Y (INVx1_ASAP7_75t_R)
  52.94 2731.29 ^ core/int_issue_unit/_243809_/SN (FAx1_ASAP7_75t_R)
  66.17 2797.46 v core/int_issue_unit/_243810_/SN (FAx1_ASAP7_75t_R)
  35.72 2833.18 ^ core/int_issue_unit/_243811_/CON (FAx1_ASAP7_75t_R)
  22.84 2856.01 v core/int_issue_unit/_243811_/SN (FAx1_ASAP7_75t_R)
  54.98 2911.00 v core/int_issue_unit/_243812_/SN (FAx1_ASAP7_75t_R)
  40.39 2951.38 ^ core/int_issue_unit/_243813_/CON (FAx1_ASAP7_75t_R)
  17.96 2969.35 v core/int_issue_unit/_243813_/SN (FAx1_ASAP7_75t_R)
  10.77 2980.12 ^ core/int_issue_unit/_213484_/Y (INVx1_ASAP7_75t_R)
  21.30 3001.42 v core/int_issue_unit/_243828_/CON (HAxp5_ASAP7_75t_R)
  28.36 3029.78 ^ core/int_issue_unit/_243821_/CON (FAx1_ASAP7_75t_R)
  25.83 3055.61 ^ core/int_issue_unit/_123817_/Y (AND3x1_ASAP7_75t_R)
  12.95 3068.57 ^ core/int_issue_unit/_123818_/Y (AO21x1_ASAP7_75t_R)
  11.30 3079.87 v core/int_issue_unit/_123819_/Y (NAND2x1_ASAP7_75t_R)
  25.05 3104.92 v core/int_issue_unit/_123820_/Y (OR3x1_ASAP7_75t_R)
   0.00 3104.92 v core/int_issue_unit/io_dis_uops_0_ready_REG$_DFF_P_/D (DFFHQNx1_ASAP7_75t_R)
        3104.92   data arrival time

1200.00 1200.00   clock clock (rise edge)
   0.00 1200.00   clock network delay (ideal)
   0.00 1200.00   clock reconvergence pessimism
        1200.00 ^ core/int_issue_unit/io_dis_uops_0_ready_REG$_DFF_P_/CLK (DFFHQNx1_ASAP7_75t_R)
 -10.94 1189.06   library setup time
        1189.06   data required time
---------------------------------------------------------
        1189.06   data required time
        -3104.92   data arrival time
---------------------------------------------------------
        -1915.86   slack (VIOLATED)

[oharboe]

And we have lots of modules 😌

>>> write_verilog blah.v
>>> exec grep module blah.v
module BoomTile (auto_buffer_out_a_ready,
endmodule
module BoomCore (clock,
endmodule
module FpPipeline (clock,
endmodule
module IssueUnitCollapsing (clock,
endmodule
module FPUExeUnit (clock,
endmodule
module FDivSqrtUnit (clock,
endmodule
module DivSqrtRecF64ToRaw_mulAddZ31 (clock,
endmodule
module RoundAnyRawFNToRecFN_7 (io_invalidExc,
endmodule
module RoundAnyRawFNToRecFN_4 (io_invalidExc,
endmodule
module FPUUnit (clock,
endmodule
module FPU (clock,
endmodule
module MulAddRecFNToRaw_postMul (io_fromPreMul_isSigNaNAny,
endmodule
module MulAddRecFNToRaw_preMul (io_op,
endmodule
module RoundAnyRawFNToRecFN_2 (io_invalidExc,
endmodule
module FPToInt (clock,
endmodule
module RecFNToIN (io_in,
endmodule
module RecFNToIN_1 (io_in,
endmodule
module \RoundAnyRawFNToRecFN_4_fpmu.narrower.roundAnyRawFNToRecFN  (io_invalidExc,
endmodule
module MulAddRecFNToRaw_postMul_1 (io_fromPreMul_isSigNaNAny,
endmodule
module MulAddRecFNToRaw_preMul_1 (io_op,
endmodule
module RoundAnyRawFNToRecFN_3 (io_invalidExc,
endmodule
module BranchKillableQueue_11 (clock,
endmodule
module BranchKillableQueue_10 (clock,
endmodule
module \FPUUnit_fpu_exe_unit_1.FPUUnit  (clock,
endmodule
module FPU_fpu (clock,
endmodule
module \MulAddRecFNToRaw_postMul_dfma.fma.mulAddRecFNToRaw_postMul  (io_fromPreMul_isSigNaNAny,
endmodule
module \MulAddRecFNToRaw_preMul_dfma.fma.mulAddRecFNToRaw_preMul  (io_op,
endmodule
module \RoundAnyRawFNToRecFN_2_dfma.fma.roundRawFNToRecFN.roundAnyRawFNToRecFN  (io_invalidExc,
endmodule
module FPToInt_fpiu (clock,
endmodule
module RecFNToIN_conv (io_in,
endmodule
module RecFNToIN_1_narrow (io_in,
endmodule
module \RoundAnyRawFNToRecFN_4_fpmu.narrower.roundAnyRawFNToRecFN_1  (io_invalidExc,
endmodule
module \MulAddRecFNToRaw_postMul_1_sfma.fma.mulAddRecFNToRaw_postMul  (io_fromPreMul_isSigNaNAny,
endmodule
module \MulAddRecFNToRaw_preMul_1_sfma.fma.mulAddRecFNToRaw_preMul  (io_op,
endmodule
module \RoundAnyRawFNToRecFN_3_sfma.fma.roundRawFNToRecFN.roundAnyRawFNToRecFN  (io_invalidExc,
endmodule
module RegisterFileSynthesizable (clock,
endmodule
module RegisterRead (clock,
endmodule
module ALUUnit (clock,
endmodule
module ALU (io_dw,
endmodule
module IntToFPUnit (clock,
endmodule
module IntToFP (clock,
endmodule
module INToRecFN (io_signedIn,
endmodule
module INToRecFN_1 (io_signedIn,
endmodule
module BranchKillableQueue_9 (clock,
endmodule
module ALUUnit_1 (clock,
endmodule
module ALU_alu (io_dw,
endmodule
module ALUUnit_2 (clock,
endmodule
module ALU_alu_1 (io_dw,
endmodule
module \ALUUnit_1_alu_exe_unit_3.ALUUnit  (clock,
endmodule
module ALU_alu_2 (io_dw,
endmodule
module MulDiv (clock,
endmodule
module CSRFile (clock,
endmodule
module BranchMaskGenerationLogic (clock,
endmodule
module DecodeUnit (io_enq_uop_inst,
endmodule
module DecodeUnit_decode_units_1 (io_enq_uop_inst,
endmodule
module DecodeUnit_decode_units_2 (io_enq_uop_inst,
endmodule
module DecodeUnit_decode_units_3 (io_enq_uop_inst,
endmodule
module RenameStage_1 (clock,
endmodule
module RenameBusyTable_1 (clock,
endmodule
module RenameFreeList_1 (clock,
endmodule
module RenameMapTable_1 (clock,
endmodule
module IssueUnitCollapsing_2 (clock,
endmodule
module IssueSlot_32 (clock,
endmodule
module IssueSlot_32_slots_1 (clock,
endmodule
module IssueSlot_32_slots_10 (clock,
endmodule
module IssueSlot_32_slots_11 (clock,
endmodule
module IssueSlot_32_slots_12 (clock,
endmodule
module IssueSlot_32_slots_13 (clock,
endmodule
module IssueSlot_32_slots_14 (clock,
endmodule
module IssueSlot_32_slots_15 (clock,
endmodule
module IssueSlot_32_slots_16 (clock,
endmodule
module IssueSlot_32_slots_17 (clock,
endmodule
module IssueSlot_32_slots_18 (clock,
endmodule
module IssueSlot_32_slots_19 (clock,
endmodule
module IssueSlot_32_slots_2 (clock,
endmodule
module IssueSlot_32_slots_20 (clock,
endmodule
module IssueSlot_32_slots_21 (clock,
endmodule
module IssueSlot_32_slots_22 (clock,
endmodule
module IssueSlot_32_slots_23 (clock,
endmodule
module IssueSlot_32_slots_24 (clock,
endmodule
module IssueSlot_32_slots_25 (clock,
endmodule
module IssueSlot_32_slots_26 (clock,
endmodule
module IssueSlot_32_slots_27 (clock,
endmodule
module IssueSlot_32_slots_28 (clock,
endmodule
module IssueSlot_32_slots_29 (clock,
endmodule
module IssueSlot_32_slots_3 (clock,
endmodule
module IssueSlot_32_slots_30 (clock,
endmodule
module IssueSlot_32_slots_31 (clock,
endmodule
module IssueSlot_32_slots_32 (clock,
endmodule
module IssueSlot_32_slots_33 (clock,
endmodule
module IssueSlot_32_slots_34 (clock,
endmodule
module IssueSlot_32_slots_35 (clock,
endmodule
module IssueSlot_32_slots_36 (clock,
endmodule
module IssueSlot_32_slots_37 (clock,
endmodule
module IssueSlot_32_slots_38 (clock,
endmodule
module IssueSlot_32_slots_39 (clock,
endmodule
module IssueSlot_32_slots_4 (clock,
endmodule
module IssueSlot_32_slots_5 (clock,
endmodule
module IssueSlot_32_slots_6 (clock,
endmodule
module IssueSlot_32_slots_7 (clock,
endmodule
module IssueSlot_32_slots_8 (clock,
endmodule
module IssueSlot_32_slots_9 (clock,
endmodule
module RegisterFileSynthesizable_1 (clock,
endmodule
module RegisterRead_1 (clock,
endmodule
module IssueUnitCollapsing_1 (clock,
endmodule
module IssueSlot_32_slots_0 (clock,
endmodule
module IssueSlot_32_slots_1_1 (clock,
endmodule
module IssueSlot_32_slots_10_1 (clock,
endmodule
module IssueSlot_32_slots_11_1 (clock,
endmodule
module IssueSlot_32_slots_12_1 (clock,
endmodule
module IssueSlot_32_slots_13_1 (clock,
endmodule
module IssueSlot_32_slots_14_1 (clock,
endmodule
module IssueSlot_32_slots_15_1 (clock,
endmodule
module IssueSlot_32_slots_16_1 (clock,
endmodule
module IssueSlot_32_slots_17_1 (clock,
endmodule
module IssueSlot_32_slots_18_1 (clock,
endmodule
module IssueSlot_32_slots_19_1 (clock,
endmodule
module IssueSlot_32_slots_2_1 (clock,
endmodule
module IssueSlot_32_slots_20_1 (clock,
endmodule
module IssueSlot_32_slots_21_1 (clock,
endmodule
module IssueSlot_32_slots_22_1 (clock,
endmodule
module IssueSlot_32_slots_23_1 (clock,
endmodule
module IssueSlot_32_slots_3_1 (clock,
endmodule
module IssueSlot_32_slots_4_1 (clock,
endmodule
module IssueSlot_32_slots_5_1 (clock,
endmodule
module IssueSlot_32_slots_6_1 (clock,
endmodule
module IssueSlot_32_slots_7_1 (clock,
endmodule
module IssueSlot_32_slots_8_1 (clock,
endmodule
module IssueSlot_32_slots_9_1 (clock,
endmodule
module RenameStage (clock,
endmodule
module RenameBusyTable (clock,
endmodule
module RenameFreeList (clock,
endmodule
module RenameMapTable (clock,
endmodule
module Rob (clock,
endmodule
module BoomNonBlockingDCache (clock,
endmodule
module AMOALU (io_mask,
endmodule
module BoomDuplicatedDataArray (clock,
endmodule
module L1MetadataArray (clock,
endmodule
module L1MetadataArray_meta_1 (clock,
endmodule
module BoomMSHRFile (clock,
endmodule
module BoomIOMSHR (clock,
endmodule
module BoomMSHR (clock,
endmodule
module BranchKillableQueue (clock,
endmodule
module BoomMSHR_mshrs_1 (clock,
endmodule
module BranchKillableQueue_rpq (clock,
endmodule
module BoomMSHR_mshrs_2 (clock,
endmodule
module BranchKillableQueue_rpq_1 (clock,
endmodule
module BoomMSHR_mshrs_3 (clock,
endmodule
module BranchKillableQueue_rpq_2 (clock,
endmodule
module BoomMSHR_mshrs_4 (clock,
endmodule
module BranchKillableQueue_rpq_3 (clock,
endmodule
module BoomMSHR_mshrs_5 (clock,
endmodule
module BranchKillableQueue_rpq_4 (clock,
endmodule
module BoomMSHR_mshrs_6 (clock,
endmodule
module BranchKillableQueue_rpq_5 (clock,
endmodule
module BoomMSHR_mshrs_7 (clock,
endmodule
module BranchKillableQueue_rpq_6 (clock,
endmodule
module Arbiter_7 (io_in_0_ready,
endmodule
module Arbiter_5 (io_in_0_ready,
endmodule
module Arbiter_6 (io_in_0_ready,
endmodule
module BoomFrontend (clock,
endmodule
module BranchPredictor (clock,
endmodule
module BIMBranchPredictorBank (clock,
endmodule
module BTBBranchPredictorBank (clock,
endmodule
module LoopBranchPredictorColumn (clock,
endmodule
module \LoopBranchPredictorColumn_banked_predictors_0.loop.columns_1  (clock,
endmodule
module \LoopBranchPredictorColumn_banked_predictors_0.loop.columns_2  (clock,
endmodule
module \LoopBranchPredictorColumn_banked_predictors_0.loop.columns_3  (clock,
endmodule
module TageBranchPredictorBank (clock,
endmodule
module TageTable (clock,
endmodule
module TageTable_1 (clock,
endmodule
module TageTable_2 (clock,
endmodule
module TageTable_3 (clock,
endmodule
module TageTable_4 (clock,
endmodule
module TageTable_5 (clock,
endmodule
module FAMicroBTBBranchPredictorBank (clock,
endmodule
module \BIMBranchPredictorBank_banked_predictors_1.bim  (clock,
endmodule
module \BTBBranchPredictorBank_banked_predictors_1.btb  (clock,
endmodule
module \LoopBranchPredictorColumn_banked_predictors_1.loop.columns_0  (clock,
endmodule
module \LoopBranchPredictorColumn_banked_predictors_1.loop.columns_1  (clock,
endmodule
module \LoopBranchPredictorColumn_banked_predictors_1.loop.columns_2  (clock,
endmodule
module \LoopBranchPredictorColumn_banked_predictors_1.loop.columns_3  (clock,
endmodule
module \TageBranchPredictorBank_banked_predictors_1.tage  (clock,
endmodule
module TageTable_t (clock,
endmodule
module TageTable_1_t_1 (clock,
endmodule
module TageTable_2_t_2 (clock,
endmodule
module TageTable_3_t_3 (clock,
endmodule
module TageTable_4_t_4 (clock,
endmodule
module TageTable_5_t_5 (clock,
endmodule
module \FAMicroBTBBranchPredictorBank_banked_predictors_1.ubtb  (clock,
endmodule
module BranchDecode (io_inst,
endmodule
module BranchDecode_bpd_decoder0 (io_inst,
endmodule
module BranchDecode_bpd_decoder0b (io_inst,
endmodule
module BranchDecode_bpd_decoder1 (io_inst,
endmodule
module BranchDecode_bpd_decoder1_1 (io_inst,
endmodule
module BranchDecode_bpd_decoder_1 (io_inst,
endmodule
module BranchDecode_bpd_decoder_2 (io_inst,
endmodule
module BranchDecode_bpd_decoder_3 (io_inst,
endmodule
module BranchDecode_bpd_decoder_4 (io_inst,
endmodule
module BranchDecode_bpd_decoder_5 (io_inst,
endmodule
module RVCExpander (io_in,
endmodule
module RVCExpander_exp_inst0b_rvc_exp (io_in,
endmodule
module RVCExpander_exp_inst1_rvc_exp (io_in,
endmodule
module RVCExpander_exp_inst1_rvc_exp_1 (io_in,
endmodule
module RVCExpander_exp_inst_rvc_exp (io_in,
endmodule
module RVCExpander_exp_inst_rvc_exp_1 (io_in,
endmodule
module RVCExpander_exp_inst_rvc_exp_2 (io_in,
endmodule
module RVCExpander_exp_inst_rvc_exp_3 (io_in,
endmodule
module RVCExpander_exp_inst_rvc_exp_4 (io_in,
endmodule
module RVCExpander_exp_inst_rvc_exp_5 (io_in,
endmodule
module Queue_20 (clock,
endmodule
module Queue_22 (clock,
endmodule
module FetchBuffer (clock,
endmodule
module FetchTargetQueue (clock,
endmodule
module ICache (clock,
endmodule
module BoomRAS (clock,
endmodule
module TLB (clock,
endmodule
module PMPChecker (io_prv,
endmodule
module LSU (clock,
endmodule
module NBDTLB (clock,
endmodule
module PMPChecker_1 (io_prv,
endmodule
module PMPChecker_1_pmp_1 (io_prv,
endmodule
module ForwardingAgeLogic (io_addr_matches,
endmodule
module ForwardingAgeLogic_forwarding_age_logic_1 (io_addr_matches,
endmodule
module PTW (clock,
endmodule
module TLWidthWidget_9 (clock,
endmodule