riscv64: fix shift amount for shift and shiftw#77
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rhelmot merged 2 commits intoangr:masterfrom Sep 29, 2025
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if this can be accompanied with a dead-simple testcase in pyvex then I will gladly merge it! |
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Only use the lowest 6 bits for
sll,srl,sraand the lowest 5 bits forsllw,srlw,srawas shift amount, by masking the rs2 register accordingly.Fix for #76