Support of wire declaration for the instance ports.

[KyleJeong]

before (assume that user copied the port declaration to top)
input clk,
input [2:0] in_a,
input [2:0] in_b,
output reg [3:0] out_sum
module module_name (
input clk,
input [2:0] in_a,
input [2:0] in_b,
output reg [3:0] out_sum
);
...
end module
after (assume the user execute the wire declaration on top and execute the instantiation on buttom)
wire clk;
wire [2:0] in_a;
wire [2:0] in_b;
wire [3:0] out_sum;
module module_name (
.clk(clk),
.in_a(in_a),
.in_b(in_b),
.out_sum(out_sum)
);
...
end module
If we can do that in one command, it will be better definetely.

[antoinemadec]

Could you please apply the modifications i required in the issue?

[antoinemadec]

Here is what needs to be done:

1. put all the code in verilog_instance.py (do not create a new file, use a script argument instead)
2. update README and vim help accordingly
3. gw is already taken (see :help gw), maybe use ggb instead?
4. test it with typedef, packed/unpacked types etc

[KyleJeong]

OK. How about this way.
I don't know vim script itself. So please let me know how can I add wire option in *.vim files.
(I need this to test the code in local computer.)

I will start to modify verilog_instance.py to support wire declaration with the assumption that there could be argv[2]. If argv[2] ==1, wire declaration., else port mapping.

"ggb" is OK to me.

After that, we can discuss the details about README and help.

[KyleJeong]

I finished the merge (removing verilog_wire.py),
But it always calls wire declaration. Can you help me what's wrong?
This is the main change
let cmd = lnum1 . "," . lnum2 . "!" . " " . s:plugin_dir_path . "/verilog_instance.py " . g:verilog_instance_skip_last_coma . " " . s:verilog_instance_wire_declaration

if !hasmapto('VerilogInstance') && maparg('gb','n') ==# ''
let s:verilog_instance_wire_declaration = 0
xmap gb VerilogInstance
nmap gb VerilogInstance
nmap gbb VerilogInstanceLine
endif

if !hasmapto('VerilogWire') && maparg('ggb','n') ==# ''
let s:verilog_instance_wire_declaration = 1
xmap ggb VerilogInstance
nmap ggb VerilogInstance
nmap ggbb VerilogInstanceLine
endif

[antoinemadec]

@KyleJeong , I will take a look at it in a few days, don't be surprised if my responses are delayed.
Thanks!

[antoinemadec]

Oops, sorry, i completely forgot about this PR.
Will take a look at it shortly