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96afb63
Moving initialisation of GIC to loader - not working
Jan 10, 2025
146ea50
Added support for odroidc4, qemu not working due to being unable to i…
Jan 13, 2025
06dfb3d
Remove qemu GIC support and assert statement typo in loader.rs
Jan 20, 2025
ca0abe6
Added support to load multiple pagetables
Jan 28, 2025
c4b6b60
Multikernel mode can be bypassed, loader.c must be rebuilt however on…
Jan 28, 2025
881ce46
Tool now initialises each page table
Jan 29, 2025
7b64e28
Allow MMUs to take in custom page table addresses
Jan 29, 2025
deac8e6
Added Ivan's multicore patch to microkit that powers up additional co…
Jan 30, 2025
8a4db6f
Added debugging for multi image
Feb 4, 2025
d53ac5c
Support for multiple kernel headers in loader.c
Feb 14, 2025
3204aad
Added addtional header info support
Mar 7, 2025
391859e
remove a hardcoded build script
midnightveil Aug 19, 2025
2955ee3
Pushing all changes, was working on getting bootups with multiple ker…
Aug 21, 2025
128a339
Merge remote-tracking branch 'freya/august_wip' into multikernel
midnightveil Aug 22, 2025
28711ab
fix customDTS overlay path
midnightveil Aug 22, 2025
1c146dc
this technically works (the monitor absolutely breaks though)
midnightveil Aug 22, 2025
ed0ce2b
extremely dodgy working with SGIs
midnightveil Aug 27, 2025
cad36ae
fix SGI target for upstream seL4 SGI API
midnightveil Aug 27, 2025
12be50d
build_sdk: just always rm the build dir
midnightveil Sep 1, 2025
e3ce715
multikernel: progress towards QEMU, back to single multikernel for now
midnightveil Sep 2, 2025
d2cdb53
make it clear the "Kernel offset" is initial task PV offset
midnightveil Sep 2, 2025
6edc6fb
loader: fix qemu GIC addresses
midnightveil Feb 13, 2025
face8e0
loader: improve exception handling setup
Ivan-Velickovic Sep 2, 2025
5830d91
Merge remote-tracking branch 'seL4/main' into multikernel
midnightveil Sep 2, 2025
bcb9b65
Merge remote-tracking branch 'seL4/set_exception_handler' into multik…
midnightveil Sep 2, 2025
924ef4d
remove device trees
midnightveil Sep 2, 2025
9207086
tool: sanity check non-overlapping regions
midnightveil Sep 2, 2025
32d5d32
remove some more things that should have been got in the rebase
midnightveil Sep 2, 2025
434e8ea
HACKY: pass kernel paddr to boot
midnightveil Sep 2, 2025
be77718
half-broken boot
midnightveil Sep 2, 2025
bf963de
ignore errors if build dir not exist
midnightveil Sep 3, 2025
9d3da58
working ! fix the values for the page tables that the tool pages in
midnightveil Sep 3, 2025
ef4b310
microkit: pass paddr_elf_base not pv_offset for kernel
midnightveil Sep 4, 2025
1cb6778
fix waiting for irqs now both kernels "boot"
midnightveil Sep 4, 2025
e0ab5c2
make the kernel/microkit aware of how many cpus
midnightveil Sep 8, 2025
f34b837
dump untyped info expected on failure
midnightveil Sep 9, 2025
4f8354f
get single core booting
midnightveil Sep 9, 2025
6f8904c
make the tool geenerate multiple copies of the invocation data etc fo…
midnightveil Sep 9, 2025
a7e547b
commit "working" microkit
midnightveil Sep 10, 2025
5d78960
refactor microkit to reference PDs by name (mostly)
midnightveil Sep 12, 2025
c9fab31
tool: technically-working SGI support; it's a bit weird though
midnightveil Sep 12, 2025
47a07cd
SGIs now work as part of the tool
midnightveil Sep 16, 2025
bbe180b
improve report formatting for interrupt triggers
midnightveil Sep 16, 2025
a635e00
working back-and-forth cross core SGIs now in the tool
midnightveil Sep 16, 2025
4f7894d
default to core 0 if no core specified
midnightveil Sep 16, 2025
e1b7bfc
make everything work multikernel or no
midnightveil Sep 16, 2025
b768951
autogenerate the SGI IRQ numbers
midnightveil Sep 16, 2025
6081ef7
odroid use 2 nodes as well
midnightveil Sep 17, 2025
8f094ce
build microkit dev tool in debug
midnightveil Sep 17, 2025
f49d980
be more faithful to kernel boot process
midnightveil Sep 17, 2025
cb8c25e
don't recreate all folders on a rebuild only the changed
midnightveil Sep 17, 2025
51fa468
print out MPIDR on CPU boot.
midnightveil Sep 18, 2025
2f35819
HORRIBLE WIP: pass kernel boot info via an information page
midnightveil Sep 18, 2025
1bf87a5
restructure boot info regions with Indan's feedback
midnightveil Sep 19, 2025
2c88ba9
remove the old sel4.rs until I actually use it
midnightveil Sep 22, 2025
a60bc33
technically working multikernel memory
midnightveil Sep 22, 2025
5bb96a3
temporary: dont test tool
midnightveil Sep 23, 2025
ebc5cea
use btreemap as this guarantees ordering (that is useful)
midnightveil Sep 23, 2025
18c0756
stop using implicit iteration ids for pds
midnightveil Sep 23, 2025
dd71030
fixup GIC init by copying kernel code
midnightveil Sep 23, 2025
917d8ab
upstream kernel bug? config should be from 32 not 64
midnightveil Sep 23, 2025
d75a264
add (BROKEN) timer example for multikernel
midnightveil Sep 23, 2025
e0236eb
shared memory timer
midnightveil Sep 23, 2025
ebde33f
"techincally works" cross-core shared mem
midnightveil Sep 23, 2025
beb8c1b
only create MR for the cores they are used in
midnightveil Sep 23, 2025
dcc06de
allocate a valid phys addr for shared accrsos creos
midnightveil Sep 23, 2025
4246962
HACK: zero out memory
midnightveil Sep 23, 2025
10bf0d9
remove hardcoding of addreses on multikernel_memory
midnightveil Sep 24, 2025
aefe96f
properly feature-flag the gic init
midnightveil Sep 24, 2025
43d7866
switch from "core" to "cpu" to match the smp code
midnightveil Sep 24, 2025
10dee58
loader: handle overflow panics
midnightveil Sep 29, 2025
0618572
create bootinfo in the tool and add it in
midnightveil Sep 29, 2025
b108b43
don't hardcode kernel entrypoint
midnightveil Sep 29, 2025
a589d95
don't hardcode the shared mem address
midnightveil Sep 29, 2025
c5b1691
remove some odroidc4-specific writes
midnightveil Sep 29, 2025
c4f759d
fix tests building
midnightveil Sep 29, 2025
4ba756b
loader: path fix
Ivan-Velickovic Sep 29, 2025
b12274d
tool: fix for older rustc versions
Ivan-Velickovic Sep 29, 2025
f301769
remove the zeroing that I accidentally readded
midnightveil Sep 29, 2025
6dc07af
tool: don't crash when no PDs on a certain core
midnightveil Sep 29, 2025
6555681
tool: give nice errors for invalidate system files
midnightveil Sep 29, 2025
4e32f3a
tool: print out all cross-core notifications if not enough SGIs
midnightveil Sep 30, 2025
51d8baa
tool: fix off-by-1 in number of available SGIs
midnightveil Sep 30, 2025
fa40b7a
tool: give each core 256MiB instead of 16MiB
midnightveil Sep 30, 2025
70ce9a9
tool: print out how many objects if allocating in batch
midnightveil Sep 30, 2025
22f690c
tool: rustfmt
midnightveil Sep 30, 2025
97c01c1
tool: make overlapping regions check print more useful information
midnightveil Sep 30, 2025
a71662b
loader: move the link address further up
midnightveil Sep 30, 2025
6a25412
Revert "tool: give each core 256MiB instead of 16MiB"
midnightveil Sep 30, 2025
59c8ab4
Revert "loader: move the link address further up"
midnightveil Sep 30, 2025
8d4ebea
tool: choose kernel memory for all kernels initially then pass down
midnightveil Sep 30, 2025
936abf0
tool: reserve other kernel memories
midnightveil Sep 30, 2025
b0a7328
reduce amount of memory for core because odroid can't do more (For now)
midnightveil Sep 30, 2025
d0e9b18
tool: allocate each kernel roughly equal amounts of memory
midnightveil Oct 1, 2025
b5dce56
loader: zero out the memory used by "device" shared memory before eac…
midnightveil Oct 1, 2025
1ab87c5
tool: style reorganise
midnightveil Oct 1, 2025
f04fa97
tool: handle both GICv3 and GICv2 number of SGIs
midnightveil Oct 1, 2025
5a04b85
tool: use CpuCore newtype in more places
midnightveil Oct 1, 2025
d4c343d
tool: update SGI generation to support {NUM_SGI} receivers per core
midnightveil Oct 1, 2025
e249f13
tool: complain if cpu > num multikernels
midnightveil Oct 1, 2025
35dc7f4
tool: turn a silent failure into an assertion
midnightveil Oct 1, 2025
0600f3b
tool: fix tests
midnightveil Oct 1, 2025
4c25a16
add a patch that handles phys mem when specified across cores
midnightveil Oct 1, 2025
24cb948
gic: use official GICv2 spec names
midnightveil Oct 2, 2025
2fb09d3
microkit: add note about SGIs always enabled
midnightveil Oct 3, 2025
0dec69d
add more SGI always enabled notes
midnightveil Oct 3, 2025
1b033ff
gicv3 sgi notes
midnightveil Oct 3, 2025
a954e3b
use multikernel num cpus from kernel
midnightveil Oct 7, 2025
c3cc0b9
loader gic initialise targets to no cpus
midnightveil Oct 7, 2025
9047a12
go back to core 0 owning interrupts by default
midnightveil Oct 7, 2025
e1ea9b6
don't print backtraces this isn't useful
midnightveil Oct 7, 2025
f6cae85
switch cpu1 to have irq handler for irq code changes
midnightveil Oct 7, 2025
bea3dc9
add settargetcore support
midnightveil Oct 7, 2025
cf3c644
set target core for IRQs on other cpus
midnightveil Oct 13, 2025
5a6c938
tool: support specified phys_addr shared_mr and zeroing them
midnightveil Oct 14, 2025
7c9a0fc
tool: gicv2 supports 16 SGIs... oops
midnightveil Oct 16, 2025
c1f20ff
16 SGIs actually don't work
midnightveil Oct 16, 2025
66d390b
benchmarks: init
midnightveil Oct 21, 2025
e791cc6
benchmark: same-core signal low-to-high
midnightveil Oct 22, 2025
b4a649a
benchmark: store results to be printed out at the end
midnightveil Oct 22, 2025
4886e1c
benchmarks: add processing script
midnightveil Oct 22, 2025
166392e
benchmarks: updates to structure
midnightveil Oct 22, 2025
1e378d0
benchmark: hi to low
midnightveil Oct 22, 2025
6b1f482
benchmarks: make benchmarks not know their channel
midnightveil Oct 22, 2025
dd5e0ee
benchmark: cross core high to low
midnightveil Oct 22, 2025
0d466bd
signal 2way low->mid->high on the same core
midnightveil Oct 23, 2025
6f24ed1
2way low to high cross core test
midnightveil Oct 23, 2025
36253f5
commit the benchmarks, because why not
midnightveil Oct 23, 2025
06a167a
tool: don't remove non-normal shared memory regions from memory regions
midnightveil Oct 23, 2025
1131d0b
loader: don't hang kernels when booting, just start all of them
midnightveil Oct 23, 2025
3fe8627
use DEFAULT_KERNEL_OPTIONS_AARCH64 in the multikernel build_sdk configs
midnightveil Oct 24, 2025
e0030a8
add output to example README
midnightveil Oct 24, 2025
9a73054
make the loader & tool handle GICv3... kinda
midnightveil Oct 24, 2025
bde1331
loader: init GICv3
midnightveil Oct 24, 2025
6719685
add imx variant of the timer example
midnightveil Oct 24, 2025
df83aed
gicv2: stop printing out targetsrn
midnightveil Oct 27, 2025
69f3b50
imx timer: actually ack the irqs (oops)
midnightveil Oct 27, 2025
cc77954
pass through the mpidrs from the bootloader to the kernel
midnightveil Oct 27, 2025
5ab9ccc
bugfix: sgi_bits should be for the specific PD
midnightveil Oct 27, 2025
5b03ece
check that size() accounting for the loaderi mage is correct
midnightveil Oct 27, 2025
6333e8a
add loader overlap checks
midnightveil Oct 27, 2025
03c092f
loader: disable MMU in case uboot left it on
midnightveil Oct 28, 2025
c23c531
timerimx: ack irq after clearing status
midnightveil Oct 28, 2025
7604744
remove old patch
midnightveil Oct 28, 2025
9b3234d
fix bit definition for ARE_NS
midnightveil Oct 29, 2025
f775a4c
use kent's setup of the GIC
midnightveil Oct 29, 2025
c1d07dc
FIXME: add note about licenses I need to fix
midnightveil Oct 30, 2025
c1121a8
add a TODO with actual number of CPUs
midnightveil Oct 30, 2025
e8dec22
remove the kernel boot serialisation for-loop (again)
midnightveil Oct 30, 2025
39514c3
ack all IRQs on startup to workaround https://github.com/seL4/seL4/is…
midnightveil Oct 31, 2025
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52 changes: 50 additions & 2 deletions build_sdk.py
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@
from shutil import copy
from pathlib import Path
from dataclasses import dataclass
import shutil
from sys import executable
from tarfile import open as tar_open, TarInfo
import platform as host_platform
Expand Down Expand Up @@ -91,6 +92,7 @@ class BoardInfo:
gcc_cpu: Optional[str]
loader_link_address: int
kernel_options: KERNEL_OPTIONS
multikernels: Optional[int] = None


@dataclass
Expand Down Expand Up @@ -130,6 +132,19 @@ class ConfigInfo:
"KernelPlatform": "maaxboard",
} | DEFAULT_KERNEL_OPTIONS_AARCH64,
),
BoardInfo(
name="maaxboard_multikernel",
arch=KernelArch.AARCH64,
gcc_cpu="cortex-a53",
loader_link_address=0x50000000,
kernel_options={
"KernelPlatform": "maaxboard",
"KernelEnableMultikernelSupport": True,
# TODO: Derive from device tree?
# "KernelMultikernelNumCPUs": 4,
"KernelMultikernelNumCPUs": 2,
} | DEFAULT_KERNEL_OPTIONS_AARCH64,
),
BoardInfo(
name="imx8mm_evk",
arch=KernelArch.AARCH64,
Expand Down Expand Up @@ -185,6 +200,20 @@ class ConfigInfo:
"KernelARMPlatform": "ultra96v2",
} | DEFAULT_KERNEL_OPTIONS_AARCH64,
),
BoardInfo(
name="odroidc4_multikernel",
arch=KernelArch.AARCH64,
gcc_cpu="cortex-a55",
loader_link_address=0x20000000,
kernel_options={
"KernelPlatform": "odroidc4",
"KernelArmVtimerUpdateVOffset": False,
"KernelEnableMultikernelSupport": True,
# TODO: Derive from device tree?
# "KernelMultikernelNumCPUs": 4,
"KernelMultikernelNumCPUs": 2,
} | DEFAULT_KERNEL_OPTIONS_AARCH64,
),
BoardInfo(
name="qemu_virt_aarch64",
arch=KernelArch.AARCH64,
Expand All @@ -198,6 +227,20 @@ class ConfigInfo:
"KernelArmExportPTMRUser": True,
} | DEFAULT_KERNEL_OPTIONS_AARCH64,
),
BoardInfo(
name="qemu_virt_aarch64_multikernel",
arch=KernelArch.AARCH64,
gcc_cpu="cortex-a53",
loader_link_address=0x70000000,
kernel_options={
"KernelPlatform": "qemu-arm-virt",
"QEMU_MEMORY": "2048",
"KernelArmExportPTMRUser": True,
"KernelEnableMultikernelSupport": True,
# TODO: Derive from device tree?
"KernelMultikernelNumCPUs": 2,
} | DEFAULT_KERNEL_OPTIONS_AARCH64,
),
BoardInfo(
name="qemu_virt_riscv64",
arch=KernelArch.RISCV64,
Expand Down Expand Up @@ -424,7 +467,9 @@ def build_sel4(
) -> Dict[str, Any]:
"""Build seL4"""
build_dir = build_dir / board.name / config.name / "sel4"
build_dir.mkdir(exist_ok=True, parents=True)
# clear to remove the cmake cache
shutil.rmtree(build_dir, ignore_errors=True)
build_dir.mkdir(parents=True)

sel4_install_dir = build_dir / "install"
sel4_build_dir = build_dir / "build"
Expand Down Expand Up @@ -719,7 +764,7 @@ def main() -> None:

if not args.skip_tool:
tool_target = root_dir / "bin" / "microkit"
test_tool()
# test_tool()
build_tool(tool_target, args.tool_target_triple)

if not args.skip_docs:
Expand Down Expand Up @@ -748,6 +793,9 @@ def main() -> None:
raise Exception("Unexpected ARM physical address bits defines")
loader_defines.append(("PHYSICAL_ADDRESS_BITS", arm_pa_size_bits))

if (num_multikernels := sel4_gen_config.get("MULTIKERNEL_NUM_CPUS")) is not None:
loader_defines.append(("NUM_MULTIKERNELS", num_multikernels))

build_elf_component("loader", root_dir, build_dir, board, config, args.llvm, loader_defines)
build_elf_component("monitor", root_dir, build_dir, board, config, args.llvm, [])
build_lib_component("libmicrokit", root_dir, build_dir, board, config, args.llvm)
Expand Down
4 changes: 2 additions & 2 deletions dev_build.py
Original file line number Diff line number Diff line change
Expand Up @@ -81,7 +81,7 @@ def main():
if not BUILD_DIR.exists():
BUILD_DIR.mkdir()

tool_rebuild = f"cd {CWD / 'tool/microkit'} && cargo build --release"
tool_rebuild = f"cd {CWD / 'tool/microkit'} && cargo build"
r = system(tool_rebuild)
assert r == 0

Expand All @@ -90,7 +90,7 @@ def main():
make_env["MICROKIT_BOARD"] = args.board
make_env["MICROKIT_CONFIG"] = args.config
make_env["MICROKIT_SDK"] = str(release)
make_env["MICROKIT_TOOL"] = (CWD / "tool/microkit/target/release/microkit").absolute()
make_env["MICROKIT_TOOL"] = (CWD / "tool/microkit/target/debug/microkit").absolute()
make_env["LLVM"] = str(args.llvm)

# Choose the makefile based on the `--example-from-sdk` command line flag
Expand Down
78 changes: 78 additions & 0 deletions example/benchmarks/Makefile
Original file line number Diff line number Diff line change
@@ -0,0 +1,78 @@
#
# Copyright 2025, UNSW.
#
# SPDX-License-Identifier: BSD-2-Clause
#
ifeq ($(strip $(BUILD_DIR)),)
$(error BUILD_DIR must be specified)
endif

ifeq ($(strip $(MICROKIT_SDK)),)
$(error MICROKIT_SDK must be specified)
endif

ifeq ($(strip $(MICROKIT_BOARD)),)
$(error MICROKIT_BOARD must be specified)
endif

MICROKIT_CONFIG ?= benchmark

BOARD_DIR := $(MICROKIT_SDK)/board/$(MICROKIT_BOARD)/$(MICROKIT_CONFIG)

ARCH := ${shell grep 'CONFIG_SEL4_ARCH ' $(BOARD_DIR)/include/kernel/gen_config.h | cut -d' ' -f4}

ifeq ($(ARCH),aarch64)
TARGET_TRIPLE := aarch64-none-elf
CFLAGS_ARCH := -mstrict-align
else ifeq ($(ARCH),riscv64)
TARGET_TRIPLE := riscv64-unknown-elf
CFLAGS_ARCH := -march=rv64imafdc_zicsr_zifencei -mabi=lp64d
else
$(error Unsupported ARCH)
endif

ifeq ($(strip $(LLVM)),True)
CC := clang -target $(TARGET_TRIPLE)
AS := clang -target $(TARGET_TRIPLE)
LD := ld.lld
else
CC := $(TARGET_TRIPLE)-gcc
LD := $(TARGET_TRIPLE)-ld
AS := $(TARGET_TRIPLE)-as
endif

MICROKIT_TOOL ?= $(MICROKIT_SDK)/bin/microkit

IMAGES := manager.elf \
signal_low_to_hi_same_core__high.elf signal_low_to_hi_same_core__low.elf \
signal_hi_to_low__high.elf signal_hi_to_low__low.elf \
signal_2way_low_to_hi__low.elf signal_2way_low_to_hi__mid.elf signal_2way_low_to_hi__high.elf

CFLAGS := -MMD -MP -nostdlib -ffreestanding -g -O2 -Wall -Wno-unused-function -I$(BOARD_DIR)/include $(CFLAGS_ARCH)
LDFLAGS := -L$(BOARD_DIR)/lib
LIBS := -lmicrokit -Tmicrokit.ld

IMAGE_FILE = $(BUILD_DIR)/loader.img
REPORT_FILE = $(BUILD_DIR)/report.txt
SYSTEM_FILE = benchmarks.system
SYSTEM_FILE_PP = $(BUILD_DIR)/$(SYSTEM_FILE).pp

all: $(IMAGE_FILE)

$(BUILD_DIR)/%.o: %.c Makefile
$(CC) -c $(CFLAGS) $< -o $@

$(BUILD_DIR)/%.elf: $(BUILD_DIR)/%.o $(BUILD_DIR)/print.o
$(LD) $(LDFLAGS) $^ $(LIBS) -o $@

-include $(addprefix $(BUILD_DIR)/, $(IMAGES:.elf=.d))
-include $(BUILD_DIR)/print.d

$(SYSTEM_FILE_PP): $(SYSTEM_FILE)
cpp -MMD -MP $< -o $@
sed -i '/^#/d' $@

-include $(BUILD_DIR)/$(SYSTEM_FILE).d

$(IMAGE_FILE) $(REPORT_FILE): $(addprefix $(BUILD_DIR)/, $(IMAGES)) $(SYSTEM_FILE_PP)
$(MICROKIT_TOOL) $(SYSTEM_FILE_PP) --search-path $(BUILD_DIR) --board $(MICROKIT_BOARD) --config $(MICROKIT_CONFIG) -o $(IMAGE_FILE) -r $(REPORT_FILE)
38 changes: 38 additions & 0 deletions example/benchmarks/README.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,38 @@
<!--
Copyright 2025, UNSW
SPDX-License-Identifier: CC-BY-SA-4.0
-->
# Example - Benchmarks

This does basic seL4 signalling performance benchmarks.

Note that in these PDs we deliberately subvert the microkit implementation
so that we have direct control over the mechanisms at play.

## signal_low_to_hi_same_core

This is a one way benchmark, which relies on the fact that the cycle counter
is a core-local value. This means we can read the cycle count in the low
priority PD and then read it again in the high priority PD and the values will
make sense.

This measures the time from a seL4_Signal in a low priority process to the
seL4_Recv in the higher priority process, i.e. both send and receive. The
cycle counters are measured in different threads and the end time communicated
back via shared memory. This is because the next run after the signaller is the
*destination*, not the *sender*.

## signal_hi_to_low_same_core

This measures the time from a seL4_Signal in a high priority process to when
that signal returns. This is because higher priority processes will always run
above low priority, so the next running will be the *sender*. This is **different**
to the case for low to high.

## signal_2way_low_to_hi_{same,cross}_core

This is a two way benchmark, performing a low to a high invocation, then another
low to high invocation; so like low -> mid -> high. This design is aimed at
cross-core scenarios, where we don't have coherent cycle counters across cores,
so measuring the cycle count on core *A* then core *B* won't produce sensible
results, as is done in `signal_low_to_hi_same_core`.
6 changes: 6 additions & 0 deletions example/benchmarks/benchmark.csv
Original file line number Diff line number Diff line change
@@ -0,0 +1,6 @@
name,mean,stddev,min,max,runs,sum,sum_squared
signal low to high same core,971.2179,23.78885578564039,944,1689,100000,97121790,94383011894
signal high to low same core,516.18716,19.28573076485147,514,1211,100000,51618716,26682112356
signal high to low cross core,483.24771,20.14544389572733,478,1179,100000,48324771,23393418813
signal 2way low to high same core,1939.69662,29.848659946060586,1896,2678,100000,193969662,376331392014
signal 2way low to high cross core,2100.82227,35.781031316155904,2034,2911,100000,210082227,441473449233
55 changes: 55 additions & 0 deletions example/benchmarks/benchmark.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,55 @@
#pragma once

#include <microkit.h>
#include <stdint.h>

#include "config.h"
#include "pmu.h"
#include "print.h"

#define UNUSED __attribute__((unused))

/* Because we deliberately subvert libmicrokit in these examples */
#define INPUT_CAP 1
#define REPLY_CAP 4
#define DECLARE_SUBVERTED_MICROKIT() \
void notified(microkit_channel ch) {}

/* Inside a benchmark, the start-stop ch */
#define BENCHMARK_START_STOP_CH 0

#define RECORDING_BEGIN() \
pmu_enable(); \
print("BEGIN\n"); \
cycles_t sample; \
uint64_t sum = 0; \
uint64_t sum_squared = 0; \
cycles_t min = CYCLES_MAX; \
cycles_t max = CYCLES_MIN;

#define RECORDING_ADD_SAMPLE(start, end) \
/* don't let the compiler reorder these before into the benchmark */ \
asm volatile("" ::: "memory"); \
sample = (end - start); \
sum += sample; \
sum_squared += sample * sample; \
min = (sample < min) ? sample : min; \
max = (sample > max) ? sample : max;

typedef struct {
uint64_t sum;
uint64_t sum_squared;
cycles_t min;
cycles_t max;
} result_t;

#define RECORDING_END(results_ptr) \
do { \
/* TODO: cache flushes for multicore? */ \
print("END\n"); \
result_t *_results = (void *)results_ptr; \
_results->sum = sum; \
_results->sum_squared = sum_squared; \
_results->min = min; \
_results->max = max; \
} while (0)
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