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Adding updated asap7 config for NyuziProcessor design (and minor tweaks to all verilog.mk files) #2

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Merged
bgoldbug merged 1 commit into from
Jan 7, 2026
Merged

Adding updated asap7 config for NyuziProcessor design (and minor tweaks to all verilog.mk files) #2

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28 changes: 4 additions & 24 deletions designs/asap7/NyuziProcessor/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -5,33 +5,13 @@ export PLATFORM = asap7

export SYNTH_HIERARCHICAL = 1

export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_1x256_1r1w.lef \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_16x52_1r1w.lef \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_18x256_1r1w.lef \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_20x64_1r1w.lef \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_20x64_2r1w.lef \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_32x128_2r1w.lef \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_512x256_1r1w.lef \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_512x2048_1r1w.lef

export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_1x256_1r1w.lib \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_16x52_1r1w.lib \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_20x64_1r1w.lib \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_18x256_1r1w.lib \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_20x64_2r1w.lib \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_32x128_2r1w.lib \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_512x256_1r1w.lib \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_512x2048_1r1w.lib

export ABC_AREA = 1

export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc

export CORE_AREA = 5 5 655 655
export DIE_AREA = 0 0 660 660
export CORE_AREA = 3 3 500 497
export DIE_AREA = 0 0 500 497

export PLACE_DENSITY_LB_ADDON = 0.15
export PLACE_DENSITY_LB_ADDON = 0.22

export MACRO_PLACE_HALO = 5 5
export MACRO_PLACE_HALO = 6 6

export TNS_END_PERCENT = 100
13 changes: 8 additions & 5 deletions designs/asap7/NyuziProcessor/constraint.sdc
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Expand Up @@ -2,14 +2,17 @@ current_design NyuziProcessor

set clk_name clk
set clk_port_name clk
set clk_period 2400
set clk_io_pct 0.15
set clk_period 1000
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]

create_clock -name $clk_name -period $clk_period $clk_port

set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [lsearch -inline -all -regexp [all_inputs]]

set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
set outputs [lsearch -inline -all-regexp [all_outputs]]

set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [lsearch -inline -all -exact $outputs $clk_name]

set_false_path -from [get_ports reset]
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