Support for eew!=sew cases for unitstride/strided load instructions#73
Support for eew!=sew cases for unitstride/strided load instructions#73akifejaz wants to merge 12 commits intochipsalliance:mainfrom
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CI is not happy. |
Let me fix this separately in another PR, updating this PR for only load instructions. |
akifejaz
changed the title
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Hi @ksco, This PR is ready please review. |
| if int(sew) > int(float64(i.Option.XLEN)*float64(c.LMUL)) { | ||
| continue | ||
| } | ||
| emul := (float64(c.SEW) / float64(sew)) * float64(c.LMUL) * float64(nfields) |
| if emul > 8 || emul < 1./8 { | ||
| continue | ||
| } | ||
| emul = math.Max(emul, 1) // offset lmul |
| builder.WriteString(i.gLoadDataIntoRegisterGroup(vd+(nf*int(c.LMUL1)), c.LMUL1, c.SEW)) | ||
| } | ||
| builder.WriteString(i.gWriteIntegerTestData(c.LMUL1*LMUL(nfields), c.SEW, 0)) | ||
| var sew SEW = 8 // sew is data width, c.SEW is offset width |
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there is no offset width in unit-stride and constant-stride instructions.
| builder.WriteString(i.gWriteRandomData(LMUL(1))) | ||
| builder.WriteString(i.gLoadDataIntoRegisterGroup(0, LMUL(1), SEW(32))) | ||
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| vd := int(c.LMUL1) |
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I don't understand why there are so many changes in the following code. When SEW != EEW, there is only 1 thing changed, which is the EMUL.
| for nf := 0; nf < nfields; nf++ { | ||
| builder.WriteString(i.gStoreRegisterGroupIntoResultData(vd+(nf*int(c.LMUL1)), c.LMUL1, c.SEW)) | ||
| builder.WriteString(i.gMagicInsn(vd+(nf*int(c.LMUL1)), c.LMUL1)) | ||
| var sew SEW = 8 // sew is data width, c.SEW is offset width |
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there is no offset width in unit-stride and constant-stride instructions.
| if int(sew) > int(float64(i.Option.XLEN)*float64(c.LMUL)) { | ||
| continue | ||
| } | ||
| emul := (float64(c.SEW) / float64(sew)) * float64(c.LMUL) * float64(nfields) |
| if emul > 8 || emul < 1./8 { | ||
| continue | ||
| } | ||
| emul = math.Max(emul, 1) // offset lmul |
| builder.WriteString(i.gWriteRandomData(LMUL(1))) | ||
| builder.WriteString(i.gLoadDataIntoRegisterGroup(0, LMUL(1), SEW(32))) | ||
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| vd := int(c.LMUL1) |
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I don't understand why there are so many changes in the following code. When SEW != EEW, there is only 1 thing changed, which is the EMUL.
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Thanks for review, let me fix these. |
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ping |
2 participants
This MR includes Unit Stride/Stride Load templates fixes for generating EEW!=SEW test cases as discussed in #72
This is my first PR & I've tried my best to follow the flow of code to match with rest of the templates. In case of any issues please let me know, I'll be happy to assist.
Best,
Akif