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Add USB 1.1 FS device#13

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ZenithalHourlyRate wants to merge 7 commits intomainfrom
usb
Open

Add USB 1.1 FS device#13
ZenithalHourlyRate wants to merge 7 commits intomainfrom
usb

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@ZenithalHourlyRate
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The info about the device itself is in the commit message.

I have personally tested it to be working, but unfortunately, there is no vigorous test for it. A vigorous test for this means substantial work and I did not have that bandwidth at that time and now.

As for the merge policy, as far as I can tell there is no merge policy for this repo. I'm willing to contribute this RTL to chipsalliance as this eases the burden of maintenance, but I have no clue what else should be done.

This PR may not get merged and anyone interested may test it and report the status here.

A USB 1.1 Full speed device is implemented.
Actually it is USB 2.0 compliant as additional requests
can be handled in software, but to make things
less confusing we say it is USB 1.1.

It is an end-to-end solution, as it can be easily
attached to the tilelink/axi4 bus and in the end
it outputs two top io for RX/TX.

The controller and PHY is not strictly separated,
and it does not have a standard UTMI/ULPI port.
The MMIO port is also custom.

The architecture for it may be found in slides
of RVSC22[1].

The driver for it may be found in [2].
Some part of the driver is quite similar
to tinyUSB so it may get ported there.

It has been verified in an Arty100t FPGA,
capable of running the required USB stack
of canokey (a yubikey alternative) [1].

The control, bulk and interrupt transfer types
worked, but the support of isoc
transfer is not added.

[1] https://github.com/OpenRigil/rvsc22
[2] https://github.com/OpenRigil/openrigil-firmware
@jiegec
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jiegec commented Mar 13, 2023

Do you consider adding UTMI(+) IO support?

@ZenithalHourlyRate
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Do you consider adding UTMI(+) IO support?

I wanted to add them a long time ago but I'm afraid there is no ETA for it

@sequencer
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sequencer commented Mar 13, 2023

We have sent out the first PCB board to JLC today, I'll approve the RTL after the FPGA test.

@ZenithalHourlyRate
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We have sent out the first PCB board to JLC today

It works with such FMC board. Great thanks to @vowstar for designing the board!

I've tested USB enumeration and USB reset and they worked. I will test bulk transfer with large payload and interrupt transfer later once I get an SPI flash installed on the FMC.

Will update the PR with minor fixes so do not merge yet.

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3 participants