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In current approach, module class TLB(
instruction: Boolean,
lgMaxSize: Int,
cfg: TLBConfig,
edge: TLEdgeOut,
pmpGranularity: Int,
pgLevels: Int,
minPgLevels: Int,
pgLevelBits: Int,
pgIdxBits: Int,
vpnBits: Int,
ppnBits: Int,
vaddrBits: Int,
vaddrBitsExtended: Int,
paddrBits: Int,
hypervisorExtraAddrBits: Int,
asIdBits: Int,
xLen: Int,
cacheBlockBytes: Int,
usingHypervisor: Boolean,
usingVM: Boolean,
usingAtomics: Boolean,
usingAtomicsInCache: Boolean,
usingAtomicsOnlyForIO: Boolean,
usingDataScratchpad: Boolean) extends Module with MemoryOpConstants {Is this a potential problem or it is acceptable? |
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What has not been done in this PR:
The former two tasks may be suitable for other new PRs. And I cannot figure out a decent solution for the last task. |
rocket/src/TLB.scala
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| instruction: Boolean, | ||
| lgMaxSize: Int, | ||
| cfg: TLBConfig, | ||
| edge: TLEdgeOut, // TODO: Decoupled from Tilelink |
| @@ -0,0 +1,136 @@ | |||
| // See LICENSE.SiFive for license details. | |||
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move it to utils and deprecate it with BitSet
| class TLB( | ||
| instruction: Boolean, | ||
| lgMaxSize: Int, | ||
| cfg: TLBConfig, |
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actually parameter below are all TLBConfig, but OK for now.
rocket/src/TLB.scala
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| val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) | ||
| val mpu_priv = Mux[UInt](usingVM.B && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S.U, Cat(io.ptw.status.debug, priv)) | ||
| val pmp = Module(new PMPChecker(lgMaxSize)) | ||
| val pmp = Module(new PMPChecker(lgMaxSize)) // TODO: Dependent on PMP |
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I don't understand comments here.
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To make it work, it requires refactor on PMP. So it won't pass compilation until PMP is migrated.
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OK this PR depends on PMP refactor now.
rocket/src/TLBPermissions.scala
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| require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") | ||
| require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") | ||
| require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") | ||
| val permissions = memParameters.foreach { p => |
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basically it should be decouple from TileLink, but OK for now...
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Is it necessary to move refactor of files like |
rocket/src/TLB.scala
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| val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) | ||
| val mpu_priv = Mux[UInt](usingVM.B && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S.U, Cat(io.ptw.status.debug, priv)) | ||
| val pmp = Module(new PMPChecker(lgMaxSize)) | ||
| val pmp = Module(new PMPChecker(lgMaxSize)) // TODO: Dependent on PMP |
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OK this PR depends on PMP refactor now.
OK~ |
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