Migrate RVC, BTB, IBuf to rocket

.github/workflows/ci.yml

@@ -0,0 +1,41 @@
+# This file describes the GitHub Actions workflow for continuous integration of rocket-chip.
+#
+# See
+# https://help.github.com/en/actions/reference/workflow-syntax-for-github-actions
+# for API reference documentation on this file format.
+
+name: Mill Continuous Integration
+env:
+  USER: runner
+
+on:
+  push:
+    branches:
+      - split
+  pull_request:
+    branches:
+      - split
+
+jobs:
+  riscv-test:
+    name: riscv-tests
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        config: [rv32, rv64]
+    steps:
+      - uses: actions/checkout@v2
+        with:
+          submodules: 'true'
+
+      - uses: cachix/install-nix-action@v19
+        with:
+          install_url: https://releases.nixos.org/nix/nix-2.13.3/install
+          nix_path: nixpkgs=channel:nixos-unstable
+
+      - name: Coursier Cache
+        uses: coursier/cache-action@v5
+
+      - name: run riscv-tests
+        run: |
+          nix --experimental-features 'nix-command flakes' develop -c mill -i -j 0 tests.riscvtests.run[${{ matrix.config }}]

build.sc

@@ -227,6 +227,10 @@ object cosim extends Module {
 
   class emulator(xLen: String) extends Module {
 
+    val ncores: Int = Runtime.getRuntime.availableProcessors()
+
+    val emulatorCores: Int = if(ncores > 8) 8 else ncores
+
     val topName = "TestBench"
 
     def sources = T.sources(millSourcePath)
@@ -291,7 +295,7 @@ object cosim extends Module {
          |  TOP_MODULE TestBench
          |  PREFIX VTestBench
          |  OPT_FAST
-         |  THREADS 8
+         |  THREADS ${emulatorCores}
          |  VERILATOR_ARGS ${verilatorArgs().mkString(" ")}
          |)
          |""".stripMargin
@@ -468,6 +472,7 @@ object tests extends Module() {
           PathRef(if (p.exitCode != 0) {
             os.move(T.dest / s"$name.running.log", T.dest / s"$name.failed.log")
             System.err.println(s"Test $name failed with exit code ${p.exitCode}")
+            System.exit(1)
             T.dest / s"$name.failed.log"
           } else {
             os.move(T.dest / s"$name.running.log", T.dest / s"$name.passed.log")

cosim/elaborate/src/DUT.scala

@@ -69,7 +69,7 @@ class DUT(xLen:Int)(p: Parameters) extends Module {
     val resetVector = InModuleBody {
       resetVectorNode.makeIO()
     }
-    val hartidNode = BundleBridgeSource(() => UInt(4.W))
+    val hartidNode = BundleBridgeSource(() => UInt(1.W))
     rocketTile.hartIdNode := hartidNode
     InModuleBody {
       hartidNode.bundle := 0.U

diplomatic/src/rocket/BaseTile.scala

@@ -3,16 +3,15 @@
 package org.chipsalliance.rockettile
 
 import Chisel._
-
+import chisel3.util.log2Ceil
 import org.chipsalliance.cde.config._
 import org.chipsalliance.rocket._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
-
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
-import freechips.rocketchip.prci.{ClockSinkParameters}
+import freechips.rocketchip.prci.ClockSinkParameters
 
 case object TileVisibilityNodeKey extends Field[TLEphemeralNode]
 case object TileKey extends Field[TileParams]
@@ -70,6 +69,7 @@ trait HasNonDiplomaticTileParameters {
     require(pgLevels >= res)
     res
   }
+  def matchBits = tileParams.btb.get.nMatchBits max log2Ceil(p(CacheBlockBytes) * tileParams.icache.get.nSets)
   def asIdBits: Int = p(ASIdBits)
   def vmIdBits: Int = p(VMIdBits)
   lazy val maxPAddrBits: Int = {

diplomatic/src/rocket/Frontend.scala

@@ -30,14 +30,7 @@ class FrontendExceptions extends Bundle {
   }
 }
 
-class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
-  val btb = new BTBResp
-  val pc = UInt(vaddrBitsExtended.W)  // ID stage PC
-  val data = UInt((fetchWidth * coreInstBits).W)
-  val mask = Bits(fetchWidth.W)
-  val xcpt = new FrontendExceptions
-  val replay = Bool()
-}
+
 
 class FrontendPerfEvents extends Bundle {
   val acquire = Bool()
@@ -49,11 +42,11 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
   val clock_enabled = Input(Bool())
   val req = Valid(new FrontendReq)
   val sfence = Valid(new SFenceReq)
-  val resp = Flipped(Decoupled(new FrontendResp))
+  val resp = Flipped(Decoupled(new FrontendResp(tileParams.btb.get, vaddrBits, vaddrBitsExtended, fetchWidth, coreInstBits)))
   val gpa = Flipped(Valid(UInt(vaddrBitsExtended.W)))
-  val btb_update = Valid(new BTBUpdate)
-  val bht_update = Valid(new BHTUpdate)
-  val ras_update = Valid(new RASUpdate)
+  val btb_update = Valid(new BTBUpdate(tileParams.btb.get, fetchWidth, vaddrBits))
+  val bht_update = Valid(new BHTUpdate(tileParams.btb.get, vaddrBits))
+  val ras_update = Valid(new RASUpdate(vaddrBits))
   val flush_icache = Output(Bool())
   val npc = Input(UInt(vaddrBitsExtended.W))
   val perf = Input(new FrontendPerfEvents())
@@ -83,7 +76,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
   val icache = outer.icache.module
   require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)
 
-  val fq = withReset(reset.asBool || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) }
+  val fq = withReset(reset.asBool || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp(tileParams.btb.get, vaddrBits, vaddrBitsExtended, fetchWidth, coreInstBits), 5, flow = true))}
 
   val clock_en_reg = Reg(Bool())
   val clock_en = clock_en_reg || io.cpu.might_request
@@ -111,7 +104,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
   val s1_speculative = Reg(Bool())
   val s2_pc = RegInit(t = UInt(vaddrBitsExtended.W), alignPC(io_reset_vector))
   val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B
-  val s2_btb_resp_bits = Reg(new BTBResp)
+  val s2_btb_resp_bits = Reg(new BTBResp(tileParams.btb.get, fetchWidth, vaddrBits))
   val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken
   val s2_tlb_resp = Reg(tlb.io.resp.cloneType)
   val s2_xcpt = s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst || s2_tlb_resp.gf.inst
@@ -190,7 +183,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
   when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true.B }
 
   if (usingBTB) {
-    val btb = Module(new BTB)
+    val btb = Module(new BTB(tileParams.btb.get, fetchBytes, fetchWidth, vaddrBits, matchBits, coreInstBits))
     btb.io.flush := false.B
     btb.io.req.valid := false.B
     btb.io.req.bits.addr := s1_pc

diplomatic/src/rocket/RocketCore.scala

@@ -213,7 +213,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   val ex_reg_xcpt_interrupt  = Reg(Bool())
   val ex_reg_valid           = Reg(Bool())
   val ex_reg_rvc             = Reg(Bool())
-  val ex_reg_btb_resp        = Reg(new BTBResp)
+  val ex_reg_btb_resp        = Reg(new BTBResp(tileParams.btb.get, fetchWidth, vaddrBits))
   val ex_reg_xcpt            = Reg(Bool())
   val ex_reg_flush_pipe      = Reg(Bool())
   val ex_reg_load_use        = Reg(Bool())
@@ -231,7 +231,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   val mem_reg_xcpt_interrupt  = Reg(Bool())
   val mem_reg_valid           = Reg(Bool())
   val mem_reg_rvc             = Reg(Bool())
-  val mem_reg_btb_resp        = Reg(new BTBResp)
+  val mem_reg_btb_resp = Reg(new BTBResp(tileParams.btb.get, fetchWidth, vaddrBits))
   val mem_reg_xcpt            = Reg(Bool())
   val mem_reg_replay          = Reg(Bool())
   val mem_reg_flush_pipe      = Reg(Bool())
@@ -275,7 +275,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   val take_pc = take_pc_mem_wb
 
   // decode stage
-  val ibuf = Module(new IBuf)
+  val ibuf = Module(new IBuf(coreInstBits, usingCompressed, vaddrBits, vaddrBitsExtended, retireWidth, decodeWidth, fetchWidth, coreInstBits, tileParams.btb.get, p(XLen)))
   val id_expanded_inst = ibuf.io.inst.map(_.bits.inst)
   val id_raw_inst = ibuf.io.inst.map(_.bits.raw)
   val id_inst = id_expanded_inst.map(_.bits)