RISC-V-Team3

Team 3's work for the Instruction Architecture and Compilers (IAC) autumn term project. This is our team statement.

Team members

Find below the links to the personal statements of each member.

Member	Username	CID	Shortcode	Personal statement
Clyde Pangilinan	clydepp	02381828	cp823	Clyde's PS
Jack Hollway	Jollway	02399831	jfh223	Jack's PS
Kacper Szkalej	ks1623	02468798	ks1623	Kacper's PS
Ayush Nayee	ayushnayee01	02446190	an2223	Ayush's PS

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Repository structure

• There are individual branches: an2223, cp823/green, jfh223/blue and ks1623/red
• There are three finalised branches: single-cycle-cpu, pipelined-cpu and partially-implemented-cache
• These have slightly different features, however the cache branch is built off the pipelined processor branch.

Branch name	Branch information
single-cycle-cpu	Fully completed single-cycle processor. All instructions implemented.
pipelined-cpu	Fully completed pipelined processor. All (the same) instructions implemented.
partially-implemented-cache	Pipelined processor with partially completed/implemented cache.

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Completion table

File name	Clyde	Jack	Kacper	Ayush
add4.sv		x
addr.sv		x
mux.sv		x
pc_reg.sv		x
aludecoder.sv	x
controlunit.sv	x
decoder.sv	x
instrmem.sv	x
datamemory.sv			x
datapath.sv			x
alu.sv	p		x
regfile.sv			x
cache.sv	p	x	x	p
F1.s				x
top.sv (single cycle)				x
top.sv (pipeline)	x
top.sv (pipeline + cache)	x			x
datapath_top.sv				x
riscv_pdf_tb.cpp				x
riscv_f1_tb.cpp				x
Pipeline registers	p	x
hazard_unit.sv	x	p

x - Full contribution
p - Partial contribution

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Specification

Implemented instructions

All instructions in the RV32I base instruction set apart from Environmental instructions ecall and ebreak have been implemented. lui and auipc are implemented (as they are needed for pseudoinstructions i.e. li).
See Clyde's personal statement to see what control signals were chosen in order to implement all the instructions.

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Team/project workflow

Working on branches

• Git features and GitHub were used throughout the whole project.
• Individual work is on branches an2223, cp823/green, jfh223/blue and ks1623/red. The reference branch is main, which is occasionally pulled from. Work on these branches may look messy.
• Branches for different processor implementations created to reduce conflicts and to make work clear.
• Finished processor branches are named with - separating words.

File organisation

In each finalised branch:

• rtl: SystemVerilog (.sv) modules for the processor
• testfiles: data (.mem) files to be loaded, instructions to be run (.s) and assemble.sh (to construct program.hex)
• Testbenches and top.sv (the processor)
• doit.sh to run instructions, testbench, Vbuddy

Individual workflow

• For communication: WhatsApp group between members
• Initially, working on individual branches (mentioned above) and working on joint branches towards the end
• Updating/writing into personal statements
• Pushing and commiting work with comments for every change made
• Meeting up on campus with members to debug problems and work on stretched goals together

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Usage instructions

To connect the Vbuddy to the computer run the code below, and put the name of the device into vbuddy.cfg.

~/Documents/iac/lab0-devtools/tools/attach_usb.sh

F1 program

To run the F1.s program, just type in:

./f1.sh

This will run the riscv_f1_tb.cpp testbench and the F1 Strip program on the Vbuddy.

Probability distribution function program

To run the pdf.s program there are four steps.

• First, load into datamemory.sv the .mem file desired

$display("Loading Data mem");
$readmemh("testfiles/noisy.mem", data_array, 17'h10000); // load initial data values here!

• Assemble the program while inside the testfiles folder

./assemble.sh 5_pdf.s

• Change the number of clock cycles the testbench riscv_pdf_tb.cppstarts from (these are stated at the bottom)

// substitute where 204850 is
if (simcyc > 204850 && simcyc % 5 == 0){
  vbdPlot(top->a0, 0, 255);
  vbdCycle(simcyc);
}

• Run the testbench (in rtl/repo folder)

./pdf.sh

For the other reference programs, just assemble them (step 2) and then run ./doit.sh (step 4)

You might need to use the code below if you don't have permissions/access to use the .sh files. Replace file_name with the corresponding name.

chmod u+r+x file_name.sh

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Working evidence

Sorry for the subpar video quality!

F1

f1.mp4

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pdf

Data loaded	Graph of result
Gaussian
Triangle
Noisy

gaussian.mp4

triangle.mp4

noisy.mp4