WIP: Merges for documentation and to support LIFCL 33/33U by jdavidberger · Pull Request #49 · gatecat/prjoxide

jdavidberger · 2026-01-28T14:56:35Z

The changes here are related to:

Updated documentation
Support for adding new platform types in general
Support for platforms LIFCL 33/33U
Somewhat faster fuzzing -- mostly by cacheing more things

- Added support for related BELs - Added support to parse compressed bitstreams - Support new device attributes - Support serializing deltas for checkpoint / debugging

…tas; refactor logic for tiletypes which configure adjacent tiles

…nd improved UI

… routing

gatecat · 2026-01-28T16:05:53Z

docs/bels/overview.md

+
+A given bel might span over multiple logical tiles. It's anchor tile is the one with the appropriate tiletype but for routing information on where the related tile is there is rel_x and rel_y; which encode the relative tile offset for the related tile. This data can be varied based on the family, device and actual tile in question. 
+
+For bels with these offsets, the offset information is used in fuzzing the routing to map the interconnect. The offset themselves can be devined from the output of the dev_get_nodes command and report for nearby CIB tiles. For instance, related tiles to LRAM will have LRAM_CORE wires in their tile. 


nitpick: derived

gatecat · 2026-01-28T16:06:39Z

docs/general/cacheing.md

+The bitstreams are stored compressed and libprjoxide can read them compressed. Instead of copying the files around, the
+cache fetch generates symbolic links. 
+
+This folder should be cleared very rarely.


most notably it needs to be cleared if you want to switch radiant version

I did not realize this. I think it makes sense to make the radiant version as part of the hash path. I'll probably make it check both old and new too so my current cache isn't burnt

That sounds like a good plan

gatecat · 2026-01-28T16:11:17Z

docs/database.md

+This serves as a master listing of each device and metadata associated with that device:
+
+- packages: Comes from various lattice documentation, can also be seen by looking at the radiant device selection dialog.
+- frame metadata: There are various necessary peices of data here. All are available in the "sysCONFIG Guide for Nexus Platform" document from the lattice website.


might be nice to expand this a bit more?

gatecat · 2026-01-28T16:12:28Z

fuzzers/LFCPNX/shared/empty_40.v

@@ -0,0 +1,9 @@
+
+(* \db:architecture ="LFCPNX", \db:device ="LFCPNX-40", \db:package ="LFG672", \db:speed ="7_High-Performance_1.0V", \db:timestamp =1576073342, \db:view ="physical" *)


huh, is there an LFCPNX-40 device?

gatecat · 2026-01-28T16:13:55Z

fuzzers/LIFCL/001-plc-routing/fuzzer.py


-cfg = FuzzConfig(job="PLCROUTE", device="LIFCL-40", sv="../shared/route_40.v", tiles=["R16C22:PLC"])
+def run_cfg(device):
+    tile = list(tiles.get_tiles_by_tiletype(device, "PLC").keys())[0]


there was a degree of caution not to pick a tile too close to the edge of the device because that could falsely cause some extra edge routing to be included, have you checked this?

gatecat · 2026-01-28T16:37:40Z

libprjoxide/prjoxide/src/bels.rs

+                "PIOA.SEIO18.BASE_TYPE" => vec![Bel::make_seio18(0)],
+                "PIOB.SEIO18.BASE_TYPE" => vec![Bel::make_seio18(1)],
+                "PIOA.DIFFIO18.BASE_TYPE" => vec![Bel::make_diffio18()],
+                "PIOB.DIFFIO18.BASE_TYPE" => vec![Bel::make_diffio18()],


I don't think PIOB.DIFFIO18 should ever happen?

I don't think so either, will remove

gatecat · 2026-01-28T16:38:36Z

libprjoxide/prjoxide/src/bitstream.rs

            if in_metadata && self.check_preamble(&COMMENT_END) {
                if curr_meta.len() > 0 {
                    self.metadata.push(curr_meta.to_string());
+ 		    if curr_meta.is_ascii() {


looks like spaces and tabs got mixed here?

gatecat · 2026-01-28T16:43:52Z

tools/extract_tilegrid.py

    if dev == "LFCPNX-100":
        return tap_frame_to_col_100
-    elif dev == "LIFCL-40" or dev == "LFDN2X-40":
+    elif dev == "LIFCL-40" or dev == "LFDN2X-40" or dev == "LFD2NX-40":


looks like LFD2NX-40 got duplicated here

gatecat · 2026-01-28T16:57:15Z

util/fuzz/primitives.py

+        self.name = name
+        self.desc = desc
+        self.depth = depth
+        self.enable_value = enable_value


might be worth documenting what "enable_value" actually means/does?

gatecat · 2026-01-28T17:00:57Z

util/fuzz/primitives.py

+    PinSetting(name="ENCLKOS4", dir="in", desc="Enable E output (CLKOS4). Active high. PLL CIB input.", bits=None),
+    PinSetting(name="ENCLKOS5", dir="in", desc="Enable F output (CLKOS5). Active high. PLL CIB input.", bits=None),
+    PinSetting(name="FBKCK", dir="in", desc="", bits=None),
+    PinSetting(name="LEGACY", dir="in", desc="PLL legacy mode signal. Active high to enter the mode. Enabled by lmmi_legacy fuse. PLL CIB input.", bits=None),


I think we shouldn't scrape descriptions from the lattice html unfortunately. It creates a theoretical copyright issue (as this is text rather than just a raw fact about an FPGA) particularly when they often reference weird lattice internal things, even if they're public facing docs.

jdavidberger added 19 commits January 5, 2026 22:33

Document some of how the database is laid out

8faaa3a

Update scripting for 2023-2025 radiant

6e60732

Add bel overview

4e3472d

Add docs

54656f3

Changes to prjoxide to support lifcl-33 devices.

dddc797

- Added support for related BELs - Added support to parse compressed bitstreams - Support new device attributes - Support serializing deltas for checkpoint / debugging

Changes related to bringing support for lifcl-33 devices

b8de947

Changes around IO for lifcl-33

5e3c9c5

Fix undriven signal warning

daae938

Remove debug code

9393828

Add support for some 33u

80e9a27

Fix 110

853b293

Incorporate env logger and py logger. Add more methods for adding del…

d6b924f

…tas; refactor logic for tiletypes which configure adjacent tiles

Gitignore / docs

39d0398

Add node database, add futures / async support, misc util functions a…

08f9b43

…nd improved UI

Make sure to print error and exit with error code if an error exists

387f835

Updated fuzzers; add support for 33u OSCD, improved general tile/site…

75cf8b6

… routing

Fix borrow issues with db; docs

ace51a1

Docs; examples

1926dd0

Merge in upstream

eedca4a

jdavidberger changed the title ~~Merges for documentation and to support LIFCL 33/33U~~ WIP: Merges for documentation and to support LIFCL 33/33U Jan 28, 2026

gatecat reviewed Jan 28, 2026

View reviewed changes


		A given bel might span over multiple logical tiles. It's anchor tile is the one with the appropriate tiletype but for routing information on where the related tile is there is rel_x and rel_y; which encode the relative tile offset for the related tile. This data can be varied based on the family, device and actual tile in question.

		For bels with these offsets, the offset information is used in fuzzing the routing to map the interconnect. The offset themselves can be devined from the output of the dev_get_nodes command and report for nearby CIB tiles. For instance, related tiles to LRAM will have LRAM_CORE wires in their tile.

		@@ -0,0 +1,9 @@

		(* \db:architecture ="LFCPNX", \db:device ="LFCPNX-40", \db:package ="LFG672", \db:speed ="7_High-Performance_1.0V", \db:timestamp =1576073342, \db:view ="physical" *)

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jdavidberger commented Jan 28, 2026

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