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arbiters

1. Fixed Priority Arbiter

Simple arbiter which grants access to the highest-priority requester that is active.

Source file: Fixed Priority Arbiter

2. Time Division Multiplexed (TDM) Arbiter

Arbiter which grants access to a requester only in fixed, pre-defined time slots regardless of request activity.

Source file: Time Division Multiplexed (TDM) Arbiter

3. Round Robin (RR) Arbiter

Arbiters grants active requesters in circular queue order, to provide basic fairness to every requester.

Source file: Round Robin Arbiter

4. Weighted Round Robin (WRR) Arbiter

Similar to RR Arbiter, but extends the round robin scehduling by assigning pre-defined weights per-requester, allowing some to receive multiple consecutive grants.

Source file: Weighted Round Robin Arbiter

5. Interleaved Weighted Round Robin (IWRR) Arbiter

Similar to WRR Arbiter, but interleaves the grants across requesters according to their weights, reducing latency and avoiding long service bursts for any single requester.

Source file: Interleaved Weighted Round Robin Arbiter

6. Deficit Round Robin (DRR) Arbiter

Arbiter which uses per-requester deficit counters to fairly schedule variable-sized packets while maintaining proportional bandwidth.

Source file: Deficit Round Robin Arbiter

License

All codes are fully synthesizable and tested. All are open-source codes, free to use, modify and distribute without any conflicts of interest with the original developer.

Developer

Mitu Raj, iammituraj@gmail.com, chip@chipmunklogic.com

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A set of different arbiters designed in Verilog/System Verilog.

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