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The wishbone and memory allocation code for ROM validated that the CPU reset address was witin the ROM address range. This however only really worked when the cpu_reset_address was 0. A second issue was that the size of the allocated memory mapping was wrongly calculated. Signed-off-by: Kees Jongenburger <kees.jongenburger@gmail.com>
keesj
commented
Feb 1, 2019
| raise ValueError( | ||
| "CPU reset address 0x{:x} is not equal to the rom start addres 0x{:x}" | ||
| .format(self.cpu_reset_address,self.mem_map["rom"])) | ||
| self.add_memory_region("rom", self.mem_map["rom"],rom_size) |
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I validated that this code now allows to map the rom section to a different address and that the code still works and believe all comments stated where resolved.
sbourdeauducq
suggested changes
Feb 6, 2019
| raise ValueError( | ||
| "CPU reset address 0x{:x} is not equal to the rom start addres 0x{:x}" | ||
| .format(self.cpu_reset_address,self.mem_map["rom"])) | ||
| self.add_memory_region("rom", self.mem_map["rom"],rom_size) |
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Style issues:
!=and notnot ==- space after comma
I believe that many targets and ARTIQ in particular have a reset address within the ROM (beginning of the ROM is the FPGA bitstream), so your change will break them.
If the reset address was always the ROM start, we would not need two parameters.
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Discussed in #96
The wishbone and memory allocation code for ROM validated that the CPU
reset address was witin the ROM address range. This however only really
worked when the cpu_reset_address was 0. A second issue was that the
size of the allocated memory mapping was wrongly calculated.