CNN Hardware Accelerator

A fully parameterized Convolutional Neural Network (CNN) accelerator implemented in SystemVerilog, designed for FPGA and ASIC deployment.

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Key Features

• Modular RTL design: Convolution, ReLU, MaxPooling, Flatten, GAP, and Argmax blocks
• FSM-controlled operation
• Parameterized image size, kernel size, and data width
• Supports real-image testbench for hardware-level verification
• Efficient FPGA resource utilization
• Configurable for various embedded AI workloads

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Top-Level Architecture

Figure: System-level CNN Accelerator pipeline.

Processing Flow:
Input → Convolution + ReLU → MaxPooling → Flatten → GAP → Argmax → Output

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Quick Start

# Clone the repository
git clone https://github.com/meds-uet/CNN-Accelerator.git
cd CNN-Accelerator

# Run a basic simulation (ModelSim / Questa / Vivado)
make sim

To modify global parameters, edit:

# File: rtl/cnn_defs.svh
parameter int DATA_WIDTH = 8;
parameter int IFMAP_SIZE = 128;
parameter int KERNEL_SIZE = 3;
parameter int STRIDE = 1;
parameter int PADDING = 1;

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Full Documentation

Complete documentation — including architecture theory, module descriptions, signal references, and simulation setup — is available on ReadTheDocs:

🔗 https://cnn-accelerator-docs.readthedocs.io/en/latest/

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Developed by Maktab-e-Digital Systems Lahore
Authors: Abdullah Nadeem & Talha Ayyaz
License: Apache License 2.0
Date: July/August 2025