Add CBOR transactors for UART, I2C, JTAG, SPI and SWD by imateosd · Pull Request #3 · nipo/nsl

imateosd · 2026-02-12T15:54:18Z

I2C, SPI, JTAG, SWD, UART transactors

This merge request adds new transactor implementations for I2C, SPI, JTAG, SWD and UART. It introduces new command and response formats for the transactors based in CBOR-encoded payloads. The descriptions of the encoded command and responses are in the cbor_transactor packages of each protocol library.
The transactors have AXI-Stream command/response interfaces instead of BNOC interfaces.

SPI (nsl_spi/cbor_transactor) — clock polarity/phase selection, variable word size, chip select control
I2C (nsl_i2c/cbor_transactor) — 7-bit and 10-bit addressing, read/write transactions, timeout read
JTAG (nsl_jtag/cbor_transactor) — TAP state machine control, shift-DR/IR with variable bit counts, bitbang operations, SWD-to-JTAG
CoreSight/SWD (nsl_coresight/cbor_transactor) — SWD read/write, configurable turnaround cycles, bitbang operations, waitcycles
UART (nsl_uart/transactor) — runtime-configurable baud rate, data bits, parity, stop bits, and RTS/CTS flow control

EZ-USB-FX2 interface

It also adds an AXI-Stream interface for Cypress' EZ-USB-FX2 controller in Slave FIFO mode with synchronous R/W. Three variants:

fx2_controller, for flags configured in indexed mode. [UNTESTED!]
fx2_controller_fixed_fast, for flags configured in fixed mode.
fx2_controller_fixed, for flags configured in fixed mode. It follows the read/write state machines described in the EZ-USB-FX2 manual and it's not optimized for speed.

Simulation/testing helpers

The following packages have been introduced or expanded:

nsl_amba/axi4_stream: added check_status boolean output overloads to all *_check_* functions. They are meant to be used together with the changes in nsl_simulation/logging and nsl_simulation/tests_reports.
nsl_simulation/logging: added colored log output with severity levels, added test step result aggregation with pass/fail counters.
nsl_simulation/test_reports: added generator for structured test reports for machine-parseable test results independently of backend.
nsl_simulation/shell: VHPIDIRECT-based background process execution for command execution during simulation.

Supporting library changes

nsl_amba/stream_sized: added support for sized frames (2-byte header containts the size of the frame) for AXI-Stream, equivalent to BNOC's implementation.
nsl_amba/control_status: added AXI-Stream-mapped control/status register set, similar to the one already available for BNOC.
nsl_data/cbor: added fixed-width overloads for encoding functions. Also added bstr and tstr header generation functions. Renamed "undefinite" to "indefinite" throughout.
nsl_data/bytestream: added "+" operator for byte_string concatenation.
nsl_uart/serdes: added uart_tx_no_generics and uart_rx_no_generics, which take UART configuration (baud divisor, bit count, parity, stop bits) as signal inputs instead of generics to allow runtime reconfiguration. Used by the UART transactor.

Minor bug fix

nsl_spi/io_extender: fixed data_i changes being lost when they occur during the processing of the previous value.

Automatic testing infrastructure using pytest

Added tests/conftest.py that discovers VHDL testbenches, runs GHDL simulations via make run, parses structured report.txt results and exposes each VHDL test case as a pytest item with JUnit XML output.
Added Dockerfile for the GHDL simulation environment and Jenkinsfile for CI.
Added testbenches for all five CBOR transactors, AXI-Stream sized modules, UART serdes, EZ-USB-FX2 controllers, logging, and test reports.

…er functions and change 'undefinite' to 'indefinite'

…f a test in a file

… colors for different log levels

…ults and save them in a log file

…for them

…s for testbenches

…nd/response buses and tests

…d/response buses and tests

…the processing of the previous one and chain back to back updates

…d/response buses and tests

…command/response buses and tests

… inputs and not generics to allow for runtime configuration

…nd/response buses and tests

… reports functions

nipo

Overall, this is an interesting set of changes.
The second half of the commits that are changes and fixes on files introduced in the same PR should be reordered and squashed into relevant changes.

nipo · 2026-02-19T20:28:38Z

lib/nsl_data/cbor/cbor.pkg.vhd

  -- Serializes a number, depending on sign of the value parameter, it
  -- spills a positive or negative item
  function cbor_number(value: integer) return byte_string;
+  function cbor_number(value: unsigned) return byte_string;


A signed would be better here.

nipo · 2026-02-19T20:28:51Z

lib/nsl_data/cbor/cbor.pkg.vhd

  -- with the minimum count of bytes. Passed value is the actual value
  -- (negative).
  function cbor_negative(value: integer) return byte_string;
+  function cbor_negative(value: unsigned) return byte_string;


A signed would be better here.

nipo · 2026-02-19T20:32:16Z

lib/nsl_data/cbor/cbor.pkg.vhd

Maybe splitting the undefinite -> indefinite changes from the rest would help review.

nipo · 2026-02-19T20:34:03Z

lib/nsl_simulation/logging/logging.pkg.vhd

  function to_string(level : log_level_t) return string;

+  function ansi_escape(command : character;
+                       arg0 : integer := - 1;


Please avoid space after unary -

nipo · 2026-02-19T20:37:25Z

lib/nsl_data/bytestream/bytestream.pkg.vhd

  function "and"(l, r : byte_string) return byte_string;
  function "or"(l, r : byte_string) return byte_string;
  function "xor"(l, r : byte_string) return byte_string;
+  function "+"(l, r : byte_string) return byte_string;


Concatination operator for VHDL is &, and it is implicitly defined for arrays like byte_string. Do we really need + to be basically an alias?

nipo · 2026-02-19T21:28:08Z

lib/nsl_uart/serdes/serdes.pkg.vhd

+
+  component uart_tx_no_generics is
+    generic(
+      bit_count_c : natural range 7 to 8


It could be made a runtime config as well.

nipo · 2026-02-19T21:39:27Z

lib/nsl_uart/transactor/cbor_controller.vhd

+    end case;
+  end function;
+
+  -- Lookup table function to convert divisor to baud rate


Rather than having a divisor, you may as well have an accumulator where:

on each cycle, add baud rate,

if accumulated value is more than system clock, a bit time passed, substract system clock

This is a functionality could be added in nsl_event.tick library by taking inspiration in nsl_signal_generator.frequency.frequency_generator.

nipo · 2026-02-19T21:41:57Z

tests/logging/src/Makefile

This commit could be split, reordered and squashed with relevant library changes

nipo · 2026-02-19T21:43:04Z

tests/.gitignore

 Default.wcfg
 isim1.wdb
 *.gtkw
+**/nsl_simulation/


Why ignoring this pattern?

nipo · 2026-02-19T21:45:01Z

lib/nsl_cypress/ez_usb_fx2/Makefile

should be reordered and squashed

…d flags mode and filed flags mode and tests

… configuration to run tests in CI

…port.txt if it exist before running the testbench

… the names in the actual implementation

…-side sidebands, removed by mistake

imateosd added 20 commits February 11, 2026 15:41

data/cbor: Add fixed-width encoding overloads, add bstr and tstr head…

38e973b

…er functions and change 'undefinite' to 'indefinite'

simulation: Add package to write simple test reports with the steps o…

5a8acdf

…f a test in a file

simulation/logging: Add support for colors in log prints with default…

d018110

… colors for different log levels

simulation/logging: Add functions to log and aggregate test steps res…

c29a674

…ults and save them in a log file

simulation: Add utility to run shell commands and processes and wait …

a7e21ec

…for them

data/bytestream: Add "+" function for byte_string

5ce2462

amba/axi4_stream: Add status boolean output to all the check function…

aa05bde

…s for testbenches

amba: Add AXI-Stream controlled control/status register set

e1db4a4

amba: Add "sized" support for AXI-Stream

c1d67b3

jtag/cbor transactor: Add CBOR-based transactor with AXI-Stream comma…

9a43088

…nd/response buses and tests

spi/cbor transactor: Add CBOR-based transactor with AXI-Stream comman…

466bb9c

…d/response buses and tests

spi/io extender: Fix data_i changes being lost if they happen during …

4538117

…the processing of the previous one and chain back to back updates

i2c/cbor transactor: Add CBOR-based transactor with AXI-Stream comman…

9f9d77c

…d/response buses and tests

coresight/cbor transactor: Add CBOR-based transactor with AXI-Stream …

c344d5b

…command/response buses and tests

uart/serdes: Add tx and rx components that take UART configuration as…

0145dcd

… inputs and not generics to allow for runtime configuration

uart/cbor transactor: Add CBOR-based transactor with AXI-Stream comma…

81a7be4

…nd/response buses and tests

tests/amba: Add tests for "sized" implementation in AXI-Stream

2c9e15e

tests/uart: Add test to test tx and rx with runtime UART configuration

31aee0d

tests/logging, tests/test_reports: Add tests for new logging and test…

4c3e001

… reports functions

Update gitignore

ddbf0d7

imateosd marked this pull request as ready for review February 12, 2026 15:55

nipo requested changes Feb 19, 2026

View reviewed changes

imateosd added 8 commits February 20, 2026 10:34

cypress: Add controller for Cypress' EZ-USB-FX2 Slave FIFOs in indexe…

c9d0185

…d flags mode and filed flags mode and tests

simulation/udp_socket : Make function udp_socket_recv_len impure

0ead04c

tests: Add pytest configuration to run select testbenches and Jenkins…

6b35294

… configuration to run tests in CI

cypress/ez_usb_fx2: Remove forgotten and removed files from Makefile

ee259f7

tests: Update pytest configuration

7093fe0

tests/uart: Remove wrongly committed report.txt file

96bd7a1

tests: Store stdout and stderr in test repors and delete testbench/re…

e897e7a

…port.txt if it exist before running the testbench

coresight/cbor transactor: Fix state routing for malformed commands

1bb591e

imateosd added 9 commits February 20, 2026 10:34

i2c/cbor transactor: Fix state routing for malformed commands

2048cd5

jtag/cbor transactor: Fix state routing for malformed commands

53e05b5

spi/cbor transactor: Fix state routing for malformed commands

63f658e

simulation/shell : Fix names of funcions in non-ghdl package to match…

4f57487

… the names in the actual implementation

i2c/cbor transactor: Always use nsl_amba to check TVALID and TREADY

e95d7f1

amba/axi4 stream: Add back new frame_queue_check_io with separate per…

41fb434

…-side sidebands, removed by mistake

coresight/cbor transactor: Fix typo and reset registered flag

ba330fa

cypress/fx2 controller: Fix sensitivity list

8b36613

uart/serdes: Remove unnecessary reinitialization of shift register

24e18c2

imateosd force-pushed the cbor_transactors branch from f1dce4f to 24e18c2 Compare February 20, 2026 09:34

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Add CBOR transactors for UART, I2C, JTAG, SPI and SWD#3

Add CBOR transactors for UART, I2C, JTAG, SPI and SWD#3
imateosd wants to merge 37 commits intonipo:masterfrom
imateosd:cbor_transactors

imateosd commented Feb 12, 2026

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imateosd commented Feb 12, 2026

I2C, SPI, JTAG, SWD, UART transactors

EZ-USB-FX2 interface

Simulation/testing helpers

Supporting library changes

Minor bug fix

Automatic testing infrastructure using pytest

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