Open
Conversation
| logic hold_en; | ||
|
|
||
| logic Kill_SI_pulp = (flush_i === 1'b1) || (reg_ena_i[NUM_INP_REGS-1] === 1'b1); //Guarded against X | ||
| `ifndef SYNTHESIS |
Member
There was a problem hiding this comment.
I would recommend the industry-standard //synopsys translate_on and //synopsys translate_off pragmas. Virtually all commercial synthesis tools recognise these and it avoids using yet-another Verilog macro.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
This blocks propergating value X to Kill_SI in div_sqrt_top_mvp.
Related to issue #152