fix nan box issue

[canxin121]

close:
openhwgroup/cva6#3123
openhwgroup/cva6#3124
openhwgroup/cva6#3125
openhwgroup/cva6#2449

[rgiunti]

I checked the PR performing a regression test with https://github.com/FondazioneChipsIT/cvfpu-uvm.git. The test runs 10000 random transactions with random operation, operands, FP format (between FP64 and FP32) and FP rounding mode (between RNE, RTZ, RDN and RUP) repeated for 10 different seeds where the results are compared with those given by the MPFR golden model. The test passed without errors, the PR can be merged in my opinion.

[canxin121]

I checked the PR performing a regression test with https://github.com/FondazioneChipsIT/cvfpu-uvm.git. The test runs 10000 random transactions with random operation, operands, FP format (between FP64 and FP32) and FP rounding mode (between RNE, RTZ, RDN and RUP) repeated for 10 different seeds where the results are compared with those given by the MPFR golden model. The test passed without errors, the PR can be merged in my opinion.

I also conducted extensive testing using my own differential testing framework and random instruction generation library, and the results are currently largely consistent with Spike's calculations.

[IhsaneTahir]

Hi @rgiunti, the current CVFPU UVM environment always NaN-boxes input operands. That’s why this specific bug hasn’t shown up, and also why it won’t be able to indicate whether this PR fixes the issue. I’m currently updating the UVM environment to make NaN boxing configurable, so we can first reproduce the bug and then verify whether the proposed fix works.

[rgiunti]

Hi @rgiunti, the current CVFPU UVM environment always NaN-boxes input operands. That’s why this specific bug hasn’t shown up, and also why it won’t be able to indicate whether this PR fixes the issue. I’m currently updating the UVM environment to make NaN boxing configurable, so we can first reproduce the bug and then verify whether the proposed fix works.

Hi @IhsaneTahir, yes you're right thank you for your job, please keep me updated about that.

[MikeOpenHWGroup]

@canxin121, @rgiunti and @IhsaneTahir, is it possible that the original developers of fpnew/cvfpu assumed that the host core would perform the Nan-boxing? @davideschiavone, would you have any insight about that? What does the CV32E40P do?