Modify vset*vl* insts behaviors [Work in progress]

src/arch/generic/decoder.hh

@@ -48,7 +48,6 @@ class InstDecoder : public SimObject
 
     bool instDone = false;
     bool outOfBytes = true;
-    bool stall = false;
 
   public:
     template <typename MoreBytesType>
@@ -155,15 +154,6 @@ class InstDecoder : public SimObject
      * decoder isn't ready (see instReady()).
      */
     virtual StaticInstPtr decode(PCStateBase &pc) = 0;
-
-    /**
-     * Has decoder been stalled?
-     *
-     * This method can be used to check if decoder has been stalled for
-     * some reason. If so, no more instructions can be fetch from decoder.
-     *
-     */
-    bool isStalled() { return this->stall; }
 };
 
 } // namespace gem5

src/arch/riscv/RiscvISA.py

@@ -39,8 +39,20 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.objects.BaseISA import BaseISA
+from m5.params import Param
 
 class RiscvISA(BaseISA):
     type = 'RiscvISA'
     cxx_class = 'gem5::RiscvISA::ISA'
     cxx_header = "arch/riscv/isa.hh"
+
+    vlen = Param.Int(
+        1024,
+        "VLEN: The number of bits in a single vector register, VLEN>=ELEN, "
+        "which must be a power of 2, and must be no greater than 65536."
+    )
+    elen = Param.Int(
+        64,
+        "ELEN: The maximum size in bits of a vector element that any operation"
+        " can produce or consume, ELEN>=8, which must be a power of 2."
+    )

src/arch/riscv/decoder.cc

@@ -44,22 +44,13 @@ void Decoder::reset()
 {
     aligned = true;
     mid = false;
-    vConfigDone = true;
     machInst = 0;
     emi = 0;
 }
 
 void
 Decoder::moreBytes(const PCStateBase &pc, Addr fetchPC)
 {
-    if (GEM5_UNLIKELY(!this->vConfigDone)) {
-        DPRINTF(Decode, "Waiting for vset*vl* to be executed\n");
-        instDone = false;
-        outOfBytes = false;
-        stall = true;
-        return;
-    }
-    stall = false;
 
     // The MSB of the upper and lower halves of a machine instruction.
     constexpr size_t max_bit = sizeof(machInst) * 8 - 1;
@@ -90,14 +81,6 @@ Decoder::moreBytes(const PCStateBase &pc, Addr fetchPC)
             instDone = compressed(emi);
         }
     }
-    if (instDone) {
-        emi.vl      = this->machVl;
-        emi.vtype8   = this->machVtype & 0xff;
-        emi.vill    = this->machVtype.vill;
-        if (vconf(emi)) {
-            this->vConfigDone = false; // set true when vconfig inst execute
-        }
-    }
 }
 
 StaticInstPtr
@@ -120,7 +103,7 @@ Decoder::decode(PCStateBase &_next_pc)
         return nullptr;
     instDone = false;
 
-    auto &next_pc = _next_pc.as<PCState>();
+    auto &next_pc = _next_pc.as<RiscvISA::PCState>();
 
     if (compressed(emi)) {
         next_pc.npc(next_pc.instAddr() + sizeof(machInst) / 2);
@@ -130,16 +113,12 @@ Decoder::decode(PCStateBase &_next_pc)
         next_pc.compressed(false);
     }
 
-    return decode(emi, next_pc.instAddr());
-}
+    emi.vl = next_pc.vl();
+    VTYPE vtype = next_pc.vtype();
+    emi.vtype8 = vtype.vtype8;
+    emi.vill = vtype.vill;
 
-void
-Decoder::setVlAndVtype(uint32_t vl, VTYPE vtype)
-{
-    this->machVtype = vtype;
-    this->machVl = vl;
-
-    this->vConfigDone = true;
+    return decode(emi, next_pc.instAddr());
 }
 
 } // namespace RiscvISA

src/arch/riscv/decoder.hh

@@ -52,7 +52,6 @@ class Decoder : public InstDecoder
   private:
     bool aligned;
     bool mid;
-    bool vConfigDone;
   protected:
     //The extended machine instruction being generated
     ExtMachInst emi;
@@ -90,8 +89,6 @@ class Decoder : public InstDecoder
     void moreBytes(const PCStateBase &pc, Addr fetchPC) override;
 
     StaticInstPtr decode(PCStateBase &nextPC) override;
-
-    void setVlAndVtype(uint32_t vl, VTYPE vtype);
 };
 
 } // namespace RiscvISA

src/arch/riscv/fp_inst.hh

@@ -40,5 +40,4 @@
             return std::make_shared<IllegalInstFault>("RM fault", machInst);\
         softfloat_roundingMode = rm;                                        \
 
-
 #endif // __ARCH_RISCV_FP_INST_HH__

src/arch/riscv/isa.cc

@@ -211,7 +211,7 @@ RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
 
 } // anonymous namespace
 
-ISA::ISA(const Params &p) : BaseISA(p)
+ISA::ISA(const Params &p) : BaseISA(p), vlen(p.vlen), elen(p.elen)
 {
     _regClasses.push_back(&intRegClass);
     _regClasses.push_back(&floatRegClass);
@@ -223,6 +223,15 @@ ISA::ISA(const Params &p) : BaseISA(p)
 
     miscRegFile.resize(NUM_MISCREGS);
     clear();
+
+    fatal_if(vlen > MaxVlenInBits, "RISC-V VLEN greater than %d not supported."
+        " Found VLEN of %d.",
+        MaxVlenInBits, vlen);
+    fatal_if(elen > vlen, "ELEN (%d) must be less than or equal to VLEN (%d).",
+        elen, vlen);
+    fatal_if(!isPowerOf2(vlen), "VLEN (%d) must be a power of 2.", vlen);
+    fatal_if(!isPowerOf2(elen), "ELEN (%d) must be a power of 2.", elen);
+    fatal_if(elen > 64, "ELEN > 64 is not supported.");
 }
 
 bool ISA::inUserMode() const

src/arch/riscv/isa.hh

@@ -75,6 +75,10 @@ enum class VPUStatus
 
 class ISA : public BaseISA
 {
+  private:
+    int vlen;
+    int elen;
+
   protected:
     std::vector<RegVal> miscRegFile;
 
@@ -97,6 +101,9 @@ class ISA : public BaseISA
     void setMiscRegNoEffect(int misc_reg, RegVal val);
     void setMiscReg(int misc_reg, RegVal val);
 
+    int getVlen() const { return vlen; }
+    int getElen() const { return elen; }
+
     RegId flattenRegId(const RegId &regId) const { return regId; }
     int flattenIntIndex(int reg) const { return reg; }
     int flattenFloatIndex(int reg) const { return reg; }

src/arch/riscv/isa/decoder.isa

@@ -3797,7 +3797,8 @@ decode QUADRANT default Unknown::unknown() {
                         uint64_t requested_vtype = zimm11;
 
                         Rd_ud = 0;
-                    }}, VectorConfigOp);
+                    }}, VectorConfigOp, IsControl, IsIndirectControl,
+                    IsUncondControl);
                     0x1: decode BIT30 {
                         0x0: vsetvl({{
                             uint64_t rd_bits = RD;
@@ -3806,7 +3807,8 @@ decode QUADRANT default Unknown::unknown() {
                             uint64_t requested_vtype = Rs2_ud;
 
                             Rd_ud = 0;
-                        }}, VectorConfigOp);
+                        }}, VectorConfigOp, IsControl, IsIndirectControl,
+                        IsUncondControl);
                         0x1: vsetivli({{
                             uint64_t rd_bits = RD;
                             uint64_t rs1_bits = -1;

src/arch/riscv/isa/formats/vector_conf.isa

@@ -86,11 +86,18 @@ def template VConfExecute {{
 
         xc->setMiscReg(MISCREG_VL, new_vl);
 
-        tc->getDecoderPtr()->as<Decoder>().setVlAndVtype(new_vl, new_vtype);
+        //tc->getDecoderPtr()->as<Decoder>().setVlAndVtype(new_vl, new_vtype);
+        RiscvISA::PCState newPCState;
+        set(newPCState, xc->pcState());
+        newPCState.vtype(new_vtype);
+        newPCState.vl(new_vl);
+        xc->pcState(newPCState);
+
+        xc->tcBase()->pcState(newPCState);
 
         Rd = new_vl;
 
         %(op_wb)s;
         return NoFault;
     }
-}};
+}};

src/arch/riscv/pcstate.hh

@@ -43,6 +43,7 @@
 #define __ARCH_RISCV_PCSTATE_HH__
 
 #include "arch/generic/pcstate.hh"
+#include "arch/riscv/regs/vector.hh"
 
 namespace gem5
 {
@@ -55,6 +56,8 @@ class PCState : public GenericISA::UPCState<4>
   private:
     bool _compressed = false;
     bool _rv32 = false;
+    VTYPE _vtype = 0;
+    uint32_t _vl = 0;
 
   public:
     using GenericISA::UPCState<4>::UPCState;
@@ -65,9 +68,11 @@ class PCState : public GenericISA::UPCState<4>
     update(const PCStateBase &other) override
     {
         Base::update(other);
-        auto &pcstate = other.as<PCState>();
+        auto &pcstate = other.as<RiscvISA::PCState>();
         _compressed = pcstate._compressed;
         _rv32 = pcstate._rv32;
+        _vtype = pcstate._vtype;
+        _vl = pcstate._vl;
     }
 
     void compressed(bool c) { _compressed = c; }
@@ -76,6 +81,12 @@ class PCState : public GenericISA::UPCState<4>
     void rv32(bool val) { _rv32 = val; }
     bool rv32() const { return _rv32; }
 
+    void vl(uint32_t val) { _vl = val; }
+    uint32_t vl() const { return _vl; }
+
+    void vtype(RiscvISA::VTYPE val) { _vtype = val; }
+    RiscvISA::VTYPE vtype() const { return _vtype; }
+
     bool
     branching() const override
     {
@@ -85,6 +96,16 @@ class PCState : public GenericISA::UPCState<4>
             return npc() != pc() + 4 || nupc() != upc() + 1;
         }
     }
+
+    bool
+    equals(const PCStateBase &_other) const override
+    {
+        auto &other = _other.as<RiscvISA::PCState>();
+        return _pc == other._pc \
+            && _upc == other._upc \
+            && _vl == other._vl \
+            && _vtype == other._vtype;
+    }
 };
 
 } // namespace RiscvISA

src/arch/riscv/regs/vector.hh

@@ -46,6 +46,7 @@ namespace gem5
 namespace RiscvISA
 {
 
+const unsigned MaxVlenInBits = 65536;
 constexpr unsigned NumVecElemPerVecReg = 4;
 using VecElem = uint64_t;
 constexpr size_t VLENB = NumVecElemPerVecReg * sizeof(VecElem);

src/arch/riscv/types.hh

@@ -59,7 +59,7 @@ typedef uint32_t MachInst;
 BitUnion64(ExtMachInst)
     Bitfield<63>        compressed;
     // More bits for vector extension
-    Bitfield<52, 41>    vl;
+    Bitfield<56, 41>    vl;
     Bitfield<40>        vill;
     SubBitUnion(vtype8, 39, 32) // exclude vill
         Bitfield<39> vma;

src/cpu/minor/fetch2.cc

@@ -303,16 +303,14 @@ Fetch2::evaluate()
 
         unsigned int output_index = 0;
 
-        bool fetch2_stall = false;
         /* Pack instructions into the output while we can.  This may involve
          * using more than one input line.  Note that lineWidth will be 0
          * for faulting lines */
         while (line_in &&
             (line_in->isFault() ||
                 fetch_info.inputIndex < line_in->lineWidth) && /* More input */
             output_index < outputWidth && /* More output to fill */
-            prediction.isBubble() && /* No predicted branch */
-            !fetch2_stall)
+            prediction.isBubble() && /* No predicted branch */)
         {
             ThreadContext *thread = cpu.getContext(line_in->id.threadId);
             InstDecoder *decoder = thread->getDecoderPtr();
@@ -388,7 +386,6 @@ Fetch2::evaluate()
                         line_in->lineBaseAddr + fetch_info.inputIndex);
                     DPRINTF(Fetch, "Offering MachInst to decoder addr: 0x%x\n",
                             line_in->lineBaseAddr + fetch_info.inputIndex);
-                    fetch2_stall = decoder->isStalled();
                 }
 
                 /* Maybe make the above a loop to accomodate ISAs with

src/cpu/o3/fetch.cc

@@ -1199,13 +1199,10 @@ Fetch::fetch(bool &status_change)
     auto *dec_ptr = decoder[tid];
     const Addr pc_mask = dec_ptr->pcMask();
 
-    auto fetchStall = false;
-
-    // Loop through instruction memory from the cache.
     // Keep issuing while fetchWidth is available and branch is not
     // predicted taken
     while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize
-           && !predictedBranch && !quiesce && !fetchStall) {
+           && !predictedBranch && !quiesce) {
         // We need to process more memory if we aren't going to get a
         // StaticInst from the rom, the current macroop, or what's already
         // in the decoder.
@@ -1253,7 +1250,6 @@ Fetch::fetch(bool &status_change)
                         pcOffset = 0;
                     }
                 } else {
-                    fetchStall = dec_ptr->isStalled();
                     // We need more bytes for this instruction so blkOffset and
                     // pcOffset will be updated
                     break;