Update RedMulE to recent, memory-mapped (SystemRDL) based version

Bender.local

@@ -1,6 +1,5 @@
 overrides:
   fpnew              : { git: "https://github.com/pulp-platform/cvfpu.git"             , rev: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 }
-  hci                : { git: "https://github.com/pulp-platform/hci.git"               , rev: 5a48a854573fca5bbabc1cfd4110fa4530a50ed7 }
   cv32e40p           : { git: "https://github.com/pulp-platform/cv32e40p.git"          , rev: 37a82d337ba60129c333d104c29e816d0698b53b }
   cv32e40x           : { git: "https://github.com/pulp-platform/cv32e40x.git"          , rev: a90101211048ba1a16cedbe4db963ab6e12569d7 }
   axi                : { git: "https://github.com/pulp-platform/axi.git"               , version: 0.39.5                               }

Bender.yml

@@ -24,13 +24,13 @@ package:
     - "Luca Balboni (luca.balboni10@studio.unibo.it)"
 
 dependencies:
-  redmule           : { git: "https://github.com/pulp-platform/redmule.git"           , rev: 9a1aa14be0b23f0ade84bab57e7e434397ac9876 } # branch: vi/scale_up
+  redmule           : { git: "https://github.com/pulp-platform/redmule.git"           , rev: 1eb90a872e813716c505d4cc9a0fcaf7dd3d131c } # branch: fc/ooo-mux
   cv32e40x          : { git: "https://github.com/pulp-platform/cv32e40x.git"          , rev: a90101211048ba1a16cedbe4db963ab6e12569d7 } # branch: vi/redmule_scaleup
   cv32e40p          : { git: "https://github.com/pulp-platform/cv32e40p.git"          , rev: 37a82d337ba60129c333d104c29e816d0698b53b } 
   idma              : { git: "https://github.com/pulp-platform/iDMA.git"              , rev: a6b190c7991331432afa9a2899d032bc1b176830 } # branch: vi/redmule_scaleup
   hwpe-stream       : { git: "https://github.com/pulp-platform/hwpe-stream.git"       , version: 1.6                                  }
-  hwpe-ctrl         : { git: "https://github.com/pulp-platform/hwpe-ctrl.git"         , rev: c35d5b0886ab549fb9144c3c14a4682112330e21 } # branch: yt/reqrsp
-  hci               : { git: "https://github.com/pulp-platform/hci.git"               , rev: 5a48a854573fca5bbabc1cfd4110fa4530a50ed7 } # branch: vi/redmule_scaleup
+  hwpe-ctrl         : { git: "https://github.com/pulp-platform/hwpe-ctrl.git"         , version: 3.0.0                                }
+  hci               : { git: "https://github.com/pulp-platform/hci.git"               , version: 2.3.0                                }
   cluster_icache    : { git: "https://github.com/pulp-platform/cluster_icache.git"    , rev: 917ecbf908bdaa22c5713bbcff277d142506bb16 } # branch: michaero/astral
   fpnew             : { git: "https://github.com/pulp-platform/cvfpu.git"             , rev: "pulp-v0.1.3"                            }
   fpu_ss            : { git: "https://github.com/pulp-platform/fpu_ss.git"            , rev: 8e2eff774d9d38a1e17a46bd56a0936dac9522f0 } # branch: vi/bender_manifest
@@ -83,6 +83,7 @@ sources:
       - hw/tile/fractal_sync_xif_inst_decoder.sv
       - hw/tile/obi_slave_fsync.sv
       - hw/tile/core_data_demux_eu_direct.sv
+      - hw/tile/magia_redmule_wrap.sv
       - hw/tile/magia_tile.sv
       # MAGIA DV
       - target/sim/src/tile/magia_tile_tb_pkg.sv
@@ -132,6 +133,7 @@ sources:
       - hw/tile/fractal_sync_xif_inst_decoder.sv
       - hw/tile/obi_slave_fsync.sv
       - hw/tile/core_data_demux_eu_direct.sv
+      - hw/tile/magia_redmule_wrap.sv
       - hw/tile/magia_tile.sv
       # MAGIA
       - hw/mesh/magia.sv
@@ -180,6 +182,7 @@ sources:
       - hw/tile/fractal_sync_xif_inst_decoder.sv
       - hw/tile/obi_slave_fsync.sv
       - hw/tile/core_data_demux_eu_direct.sv
+      - hw/tile/magia_redmule_wrap.sv
       - hw/tile/magia_tile.sv
       # MAGIA
       - hw/mesh/noc/floo_axi_mesh_2x2_noc.sv

Makefile

@@ -30,9 +30,11 @@ BUILD_DIR      ?= sim/work
 ifneq (,$(wildcard /etc/iis.version))
     QUESTA ?= questa-2025.1
     BENDER ?= bender
+    BASE_PYTHON ?= python
 else
     QUESTA ?=
     BENDER ?= ./bender
+    BASE_PYTHON ?= python3
 endif
 BENDER_DIR     ?= .
 ISA            ?= riscv
@@ -60,7 +62,7 @@ compile_script_synth ?= scripts/synth_compile.tcl
 compile_flag         ?= -suppress 2583 -suppress 13314 -suppress 3009
 
 questa_compile_flag  += -t 1ns -suppress 3009
-questa_opt_flag      += -suppress 3009 -debugdb +acc=npr
+questa_opt_flag      += -suppress 3009 -debugdb +acc
 questa_opt_fast_flag += -suppress 3009
 questa_run_flag      += -t 1ns -debugDB -suppress 3009
 questa_run_fast_flag += -t 1ns -suppress 3009
@@ -128,7 +130,7 @@ VSIM_LIBS=work
 $(STIM_INSTR) $(STIM_DATA): $(BIN)
 	objcopy --srec-len 1 --output-target=srec $(BIN) $(BIN).s19 &&	\
 	scripts/parse_s19.pl $(BIN).s19 > $(BIN).txt &&					\
-	python scripts/s19tomem.py $(BIN).txt $(STIM_INSTR) $(STIM_DATA)
+	$(BASE_PYTHON) scripts/s19tomem.py $(BIN).txt $(STIM_INSTR) $(STIM_DATA)
 	cd $(TEST_DIR)/$(test) &&										\
 	ln -sfn $(ROOT_DIR)/$(INI_PATH) $(VSIM_INI) &&						\
 	ln -sfn $(ROOT_DIR)/$(WORK_PATH) $(VSIM_LIBS)
@@ -159,9 +161,6 @@ IDMA_ADD_IDS ?= rw_axi_rw_obi
 # Parameters used for FlooNoC
 FLOONOC_ROOT ?= $(shell $(BENDER) path floo_noc)
 
-# Setup python3 venv and install dependencies
-BASE_PYTHON ?= python
-
 .PHONY: python_venv python_deps
 
 python_venv:
@@ -318,7 +317,7 @@ objdump:
 	$(OBJDUMP) -d -l -s $(BIN) > $(ODUMP)
 
 itb:
-	python scripts/objdump2itb.py $(ODUMP) > $(ITB)
+	$(BASE_PYTHON) scripts/objdump2itb.py $(ODUMP) > $(ITB)
 
 OP     ?= gemm
 fp_fmt ?= FP16
@@ -367,7 +366,7 @@ hw-all: hw-clean hw-lib hw-compile hw-opt
 # Nonfree components
 MAGIA_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/magia-nonfree
 MAGIA_NONFREE_DIR ?= nonfree
-MAGIA_NONFREE_COMMIT ?= main
+MAGIA_NONFREE_COMMIT ?= v0.1
 
 .PHONY: magia-nonfree-init
 MAGIA_NONFREE_DEPS ?= 1

hw/tile/converters/hci2obi.sv

@@ -30,10 +30,10 @@ module hci2obi_rsp #(
   assign obi_rsp_o.gnt                 = hci_rsp_i.gnt;
   assign obi_rsp_o.rvalid              = hci_rsp_i.r_valid;
   assign obi_rsp_o.r.rdata             = hci_rsp_i.r_data;
-  assign obi_rsp_o.r.rid               = '0;
-  assign obi_rsp_o.r.err               = 1'b0;
-  assign obi_rsp_o.r.r_optional.ruser  = 'b0;
+  assign obi_rsp_o.r.rid               = hci_rsp_i.r_id;
+  assign obi_rsp_o.r.err               = hci_rsp_i.r_opc;
+  assign obi_rsp_o.r.r_optional.ruser  = '0;
   assign obi_rsp_o.r.r_optional.exokay = 1'b0;
-  assign obi_rsp_o.r.r_optional.rchk   = 'b0;
+  assign obi_rsp_o.r.r_optional.rchk   = '0;
 
 endmodule: hci2obi_rsp

hw/tile/converters/obi2hci.sv

@@ -21,19 +21,22 @@
 
 module obi2hci_req #(
   parameter type obi_req_t = logic,
-  parameter type hic_req_t = logic
+  parameter type hci_req_t = logic
 )(
   input  obi_req_t obi_req_i,
-  output hic_req_t hci_req_o
+  output hci_req_t hci_req_o
 );
 
-  assign hci_req_o.req   = obi_req_i.req;
-  assign hci_req_o.add   = obi_req_i.a.addr;
-  assign hci_req_o.wen   = ~obi_req_i.a.we;
-  assign hci_req_o.data  = obi_req_i.a.wdata;
-  assign hci_req_o.be    = obi_req_i.a.be;
-  assign hci_req_o.boffs = '0;
-  assign hci_req_o.lrdy  = 1'b1;
-  assign hci_req_o.user  = '0;
+  assign hci_req_o.req  = obi_req_i.req;
+  assign hci_req_o.add  = obi_req_i.a.addr;
+  assign hci_req_o.wen  = ~obi_req_i.a.we;
+  assign hci_req_o.data = obi_req_i.a.wdata;
+  assign hci_req_o.be   = obi_req_i.a.be;
+  assign hci_req_o.user = '0;
+  assign hci_req_o.id   = '0;
+  assign hci_req_o.ecc  = '0;
+  assign hci_req_o.ereq = '0;
+  assign hci_req_o.r_ready = 1'b1;
+  assign hci_req_o.r_eready = '1;
 
 endmodule: obi2hci_req

hw/tile/l1_spm.sv

@@ -26,9 +26,9 @@ module l1_spm #(
   parameter int unsigned ID_W      = 1,     // ID width
   parameter              SIM_INIT  = "ones" // Simulation initialization value
 )(
-  input logic        clk_i,
-  input logic        rst_ni,
-  hci_mem_intf.slave tcdm_slave[N_BANK] // Memory interface
+  input logic         clk_i,
+  input logic         rst_ni,
+  hci_core_intf.target tcdm_slave[N_BANK] // Memory interface
 );
 
   for (genvar i = 0; i < N_BANK; i++) begin: gen_tcdm_bank
@@ -37,9 +37,12 @@ module l1_spm #(
     assign rsp_id_d           = tcdm_slave[i].id;
     assign tcdm_slave[i].r_id = rsp_id_q;
 
-    always_ff @(posedge clk_i, negedge rst_ni) begin: rsp_id_register
-      if (~rst_ni) rsp_id_q <= '0;
-      else         rsp_id_q <= rsp_id_d;
+    always_ff @(posedge clk_i or negedge rst_ni)
+    begin
+      if (~rst_ni)
+        rsp_id_q <= '0;
+      else
+        rsp_id_q <= rsp_id_d;
     end
 
     tc_sram #(
@@ -64,7 +67,13 @@ module l1_spm #(
       .rdata_o ( tcdm_slave[i].r_data                     )
     );
 
-    assign tcdm_slave[i].gnt = 1'b1;
+    assign tcdm_slave[i].gnt     = 1'b1;
+    assign tcdm_slave[i].r_valid = '1;
+    assign tcdm_slave[i].r_user  = '0;
+    assign tcdm_slave[i].r_opc   = 1'b0;
+    assign tcdm_slave[i].r_ecc   = '0;
+    assign tcdm_slave[i].egnt    = '0;
+    assign tcdm_slave[i].r_evalid = '0;
   end
 
 endmodule: l1_spm