Muchen/teranoc spatz

Bender.lock

@@ -7,8 +7,8 @@ packages:
     dependencies:
     - common_cells
   axi:
-    revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2
-    version: 0.39.2
+    revision: a256a3b86394fedf19e361047fccfdd7f6ef83e4
+    version: 0.39.9
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
@@ -24,34 +24,24 @@ packages:
     - axi
     - common_cells
     - common_verification
-  cluster_icache:
-    revision: 0e1fb6751d9684d968ba7fb40836e6118b448ecd
-    version: 0.1.1
-    source:
-      Git: https://github.com/pulp-platform/cluster_icache.git
-    dependencies:
-    - axi
-    - common_cells
-    - scm
-    - tech_cells_generic
   cluster_interconnect:
-    revision: 7d0a4f8acae71a583a6713cab5554e60b9bb8d27
+    revision: 8c6c2273d60077002834d2cb5d8e44ee0de3e32c
     version: null
     source:
       Git: https://github.com/pulp-platform/cluster_interconnect.git
     dependencies:
     - common_cells
   common_cells:
-    revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239
-    version: 1.33.0
+    revision: 9ca8a7655f741e7dd5736669a20a301325194c28
+    version: 1.39.0
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
     - common_verification
     - tech_cells_generic
   common_verification:
-    revision: 9c07fa860593b2caabd9b5681740c25fac04b878
-    version: 0.2.3
+    revision: fb1885f48ea46164a10568aeff51884389f67ae3
+    version: 0.2.5
     source:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
@@ -67,16 +57,16 @@ packages:
     - common_verification
     - idma
   fpnew:
-    revision: 9481d57c161bb160fd294eae07279082bff06698
+    revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315
     version: null
     source:
       Git: https://github.com/pulp-platform/cvfpu.git
     dependencies:
     - common_cells
     - fpu_div_sqrt_mvp
   fpu_div_sqrt_mvp:
-    revision: 917dd79cb2dc1a8f43df1a84e0e4231508a980e9
-    version: null
+    revision: 86e1f558b3c95e91577c41b2fc452c86b04e85ac
+    version: 1.0.4
     source:
       Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
     dependencies:
@@ -92,8 +82,8 @@ packages:
     - common_verification
     - register_interface
   register_interface:
-    revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19
-    version: 0.4.3
+    revision: d6e1d4cdaab7870f4faf3f88a1c788eaf5ac129d
+    version: 0.4.7
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:
@@ -109,6 +99,14 @@ packages:
     dependencies:
     - axi
     - common_cells
+  riscv-dbg:
+    revision: 122510063a02e0d012f0497ffdbafca53d4e716b
+    version: 0.7.0
+    source:
+      Git: https://github.com/pulp-platform/riscv-dbg.git
+    dependencies:
+    - common_cells
+    - tech_cells_generic
   scm:
     revision: null
     version: null
@@ -123,6 +121,21 @@ packages:
     dependencies:
     - axi
     - common_cells
+    - scm
+  spatz:
+    revision: d02afac73f586780ae5669ec9c378ef3125a0d06
+    version: null
+    source:
+      Git: https://github.com/yzf0470/spatz.git
+    dependencies:
+    - axi
+    - axi_riscv_atomics
+    - common_cells
+    - fpnew
+    - idma
+    - register_interface
+    - riscv-dbg
+    - tech_cells_generic
   tech_cells_generic:
     revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
     version: 0.2.13

Bender.yml

@@ -7,13 +7,14 @@ package:
 
 dependencies:
   axi:                  { git: "https://github.com/pulp-platform/axi.git",                  version: 0.39.2  }
-  cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", version: 1.2.1   }
+  cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: resp_wen    }
   common_cells:         { git: "https://github.com/pulp-platform/common_cells.git",         version: 1.33.0  }
   idma:                 { path: "hardware/deps/idma"                                                         }
   register_interface:   { git: "https://github.com/pulp-platform/register_interface.git",   version: 0.4.3   }
   reqrsp_interface:     { path: "hardware/deps/reqrsp_interface"                                             }
   snitch:               { path: "hardware/deps/snitch"                                                       }
-  cluster_icache:       { git: "https://github.com/pulp-platform/cluster_icache.git",       version: 0.1.1   }
+  spatz:                { git: "https://github.com/yzf0470/spatz.git",                      rev:   d02afac   }
+  # cluster_icache:       { git: "https://github.com/pulp-platform/cluster_icache.git",       version: 0.1.1   }
   tech_cells_generic:   { git: "https://github.com/pulp-platform/tech_cells_generic.git",   version: 0.2.13  }
   fpnew:                { git: "https://github.com/pulp-platform/cvfpu.git",                rev: pulp-v0.1.3 }
   floo_noc:             { git: "https://github.com/pulp-platform/FlooNoC.git",              rev: yr/adaptive_routing}
@@ -29,6 +30,7 @@ sources:
   # Level 0
   - hardware/src/mempool_pkg.sv
   - hardware/src/axi_hier_interco.sv
+  - hardware/src/tcdm_id_remapper.sv
   - hardware/src/mempool_cc.sv
   - hardware/src/snitch_addr_demux.sv
   - hardware/src/tcdm_adapter.sv
@@ -69,10 +71,10 @@ sources:
       - hardware/tb/traffic_generator.sv
       # Level 2
       - hardware/tb/mempool_tb.sv
-      # DRAMsys
-      - hardware/deps/dram_rtl_sim/src/sim_dram.sv
-      - hardware/deps/dram_rtl_sim/src/axi_dram_sim.sv
-      - hardware/deps/dram_rtl_sim/src/dram_sim_engine.sv
+      # # DRAMsys
+      # - hardware/deps/dram_rtl_sim/src/sim_dram.sv
+      # - hardware/deps/dram_rtl_sim/src/axi_dram_sim.sv
+      # - hardware/deps/dram_rtl_sim/src/dram_sim_engine.sv
 
   - target: mempool_verilator
     files:

Makefile

@@ -56,6 +56,14 @@ else
   CLANG_LDFLAGS  := ""
 endif
 
+ifeq ($(spatz), 1)
+# RV32XPULPIMG := opcodes-xpulpabs_CUSTOM opcodes-xpulpbr_CUSTOM opcodes-xpulpclip_CUSTOM opcodes-xpulpmacsi_CUSTOM opcodes-xpulpminmax_CUSTOM opcodes-xpulpslet_CUSTOM
+# RV32XPULPIMG += opcodes-xpulpbitop_CUSTOM
+	MEMPOOL_ISA := opcodes-frep_CUSTOM 
+# $(RV32XPULPIMG) opcodes-xpulppostmod_CUSTOM
+	OPCODES := "$(MEMPOOL_ISA) opcodes-rvv opcodes-smallfloat"
+endif
+
 ################
 # Dependencies #
 ################
@@ -114,7 +122,7 @@ halide:
 # Toolchain
 toolchain: toolchain-submodules tc-riscv-gcc tc-llvm riscv-isa-sim
 
-toolchain-submodules:
+toolchain-submodules: 
 	git submodule update --init --recursive
 
 tc-riscv-gcc:
@@ -267,13 +275,22 @@ apps:
 update_opcodes: software/runtime/encoding.h hardware/deps/snitch/src/riscv_instr.sv
 
 software/runtime/encoding.h: toolchain/riscv-opcodes/*
+ifeq ($(spatz), 1)
+	MY_OPCODES=$(OPCODES) make -C toolchain/riscv-opcodes encoding_out.h
+else
 	make -C toolchain/riscv-opcodes encoding_out.h
+endif
 	mv toolchain/riscv-opcodes/encoding_out.h $@
 	ln -fsr $@ toolchain/riscv-isa-sim/riscv/encoding.h
 	ln -fsr $@ software/riscv-tests/env/encoding.h #this will change when riscv-tests is a submodule
 
 hardware/deps/snitch/src/riscv_instr.sv: toolchain/riscv-opcodes/*
+ifeq ($(spatz), 1)
+	MY_OPCODES=$(OPCODES) make -C toolchain/riscv-opcodes inst.sverilog
+# 		make -C toolchain/riscv-opcodes inst.sverilog
+else
 	make -C toolchain/riscv-opcodes inst.sverilog
+endif
 	mv toolchain/riscv-opcodes/inst.sverilog $@
 
 toolchain/riscv-opcodes/*:

config/config.mk

@@ -62,10 +62,10 @@ xqueue_size ?= 0
 ################################
 
 # Enable the XpulpIMG extension
-xpulpimg ?= 1
+xpulpimg ?= 0
 
 # Enable FPU extensions
-zfinx ?= 1
+zfinx ?= 0
 
 # Enable FPU extensions
 zquarterinx ?= 0

config/floo_noc_mempool_spatz4_fpu.yml

@@ -0,0 +1,112 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: terapool
+description: "Terapool AXI NoC"
+network_type: "narrow-wide"
+
+routing:
+  route_algo: "SRC"
+  use_id_table: true
+
+protocols:
+  - name: "narrow_in"
+    type: "narrow"
+    protocol: "AXI4"
+    data_width: 64
+    addr_width: 32
+    id_width: 1
+    user_width: 1
+    direction: "input"
+  - name: "narrow_out"
+    type: "narrow"
+    protocol: "AXI4"
+    data_width: 64
+    addr_width: 32
+    id_width: 1
+    user_width: 1
+    direction: "output"
+  - name: "wide_in"
+    type: "wide"
+    protocol: "AXI4"
+    data_width: 512
+    addr_width: 32
+    id_width: 2
+    user_width: 1
+  - name: "wide_out"
+    type: "wide"
+    protocol: "AXI4"
+    data_width: 512
+    addr_width: 32
+    id_width: 2
+    user_width: 1
+
+endpoints:
+  - name: "group"
+    array: [2, 2]
+    mgr_port_protocol:
+      - "wide_in"
+  - name: "hbm"
+    array: [4]
+    addr_range:
+      base: 0x8000_0000
+      size: 0x0010_0000
+    sbr_port_protocol:
+      - "wide_out"
+  - name: "periphs"
+    addr_range:
+      - start: 0x0000_0000
+        end: 0x7FFF_FFFF
+      - start: 0xA000_0000
+        end: 0xC000_FFFF
+    sbr_port_protocol:
+      - "wide_out"
+  - name: "host"
+    mgr_port_protocol:
+      - "wide_in"
+
+routers:
+  - name: "group_router"
+    array: [2, 2]
+    degree: 5
+  - name: "periph_router"
+
+connections:
+  - src: "group"
+    dst: "group_router"
+    src_range:
+    - [0, 1]
+    - [0, 1]
+    dst_range:
+    - [0, 1]
+    - [0, 1]
+    dst_dir: "Eject"
+  # HBM West
+  - src: "hbm"
+    dst: "group_router"
+    src_range:
+    - [0, 1]
+    dst_range:
+    - [0, 0]
+    - [0, 1]
+    dst_dir: "West"
+  # HBM East
+  - src: "hbm"
+    dst: "group_router"
+    src_range:
+    - [3, 2]
+    dst_range:
+    - [1, 1]
+    - [1, 0]
+    dst_dir: "East"
+  # Attach special peripheral/HBM router to the mesh
+  - src: "periph_router"
+    dst: "group_router"
+    dst_idx: [0, 0]
+    dst_dir: "South"
+  # Attach last HBM channel and peripherals to the special router
+  - src: "periph_router"
+    dst: "periphs"
+  - src: "periph_router"
+    dst: "host"