Fix Snitch Cache Configuration, Update Memory Map, and Improve Simulation Support

.gitignore

@@ -5,6 +5,11 @@ transcript
 cheshire
 idma
 hyperbus
+snitch_cluster
+.cache
+deps/
+*.OLD
+*.egg-info/
 
 # EMACS
 
@@ -37,8 +42,12 @@ target/sim/vsim/work
 target/sim/vsim/transcript
 target/sim/vsim/*.do
 target/sim/vsim/trace*
+target/sim/vsim/dma_trace*
 modelsim.ini
 compile.tcl
 logs
 vsim.wlf
 *.transcript
+
+nonfree/
+working_dir/

Bender.yml

@@ -36,6 +36,7 @@ sources:
   - hw/bootrom/snitch/snitch_bootrom.sv
   - hw/narrow_adapter.sv
   - hw/chimera_cluster_adapter.sv
+  - hw/apb_dump_msg.sv
 
   # List of clusters
   - hw/clusters/chimera_cluster.sv

hw/apb_dump_msg.sv

@@ -0,0 +1,73 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Lorenzo Leone <lleone@iis.ee.ethz.ch>
+//
+// This module is introduced to improve the system debuggability.
+// When the target synthesis is used, teh module behaves as a bypass
+// for teh APB messages.
+// During simulation instead, the APB messages directed to teh
+// DUMP address 0x30004ffc are printed in a UART fashion on teh console.
+
+module apb_dump_msg
+  import chimera_pkg::*;
+#(
+  parameter logic        [31:0] DumpAddr  = 32'h30004ffc,
+  parameter int unsigned        DataWidth = 32
+) (
+  input  logic      clk_i,
+  input  logic      rst_ni,
+  // From Top
+  output apb_resp_t apb_rsp_o,
+  input  apb_req_t  apb_req_i,
+  // To Top
+  input  apb_resp_t apb_rsp_i,
+  output apb_req_t  apb_req_o
+);
+
+`ifdef SYNTHESIS
+  assign apb_req_o = apb_req_i;
+  assign apb_rsp_o = apb_rsp_i;
+`else
+
+  logic dump;
+
+  assign dump = apb_req_i.psel && apb_req_i.penable && apb_req_i.pwrite&&
+                (apb_req_i.paddr == DumpAddr);
+
+  always_comb begin : gen_dump
+    apb_req_o = apb_req_i;
+    apb_rsp_o = apb_rsp_i;
+    // Mask teh APB request if targetting the dump address
+    if (dump) begin : gen_mask_req
+      apb_req_o.psel    = 1'b0;
+      apb_req_o.penable = 1'b0;
+      apb_rsp_o.pready  = 1'b1;
+    end
+  end
+
+
+  // pragma translate_off
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      // no state
+    end else if (dump) begin
+      for (int unsigned i = 0; i < DataWidth / 8; i++) begin
+        // Use strobe if present; otherwise always print all bytes.
+        if (apb_req_i.pstrb[i]) begin
+          logic [7:0] ch;
+          ch = apb_req_i.pwdata[i*8+:8];
+          if (ch == 8'h0A) begin : gen_print_newline
+            $display("");
+          end else begin : gen_print_char
+            $write("%c", ch);
+          end
+        end
+      end
+    end
+  end
+  // pragma translate_on
+
+`endif
+endmodule

hw/chimera_pkg.sv

@@ -126,24 +126,27 @@ ExtClusters
 
   // Memory Island
   localparam byte_bt MemIslandIdx = ClusterIdx[ExtClusters-1] + 1;
+  // WIESEP: Address space 512 KiB
+  localparam doub_bt MemIslRegionLength = 64'h8_0000;
   localparam doub_bt MemIslRegionStart = 64'h4800_0000;
-  localparam doub_bt MemIslRegionEnd = 64'h4804_0000;
+  localparam doub_bt MemIslRegionEnd = MemIslRegionStart + MemIslRegionLength;
 
   // Size of memory island: MemIslNumWideBanks * MemIslNarrowToWideFactor * MemIslWordsPerBank * <BytesPerWord>
   // with BytesPerWord = cfg.AxiDataWidth / 8
   localparam aw_bt MemIslAxiMstIdWidth = 1;
-  localparam byte_bt MemIslNarrowToWideFactor = 16;
+  localparam byte_bt MemIslNarrowToWideFactor = 16;  // 32 bit (narrow) vs. 512 bit (wide)
   localparam byte_bt MemIslNarrowPorts = 1;
   localparam byte_bt MemIslWidePorts = $countones(ChimeraClusterCfg.hasWideMasterPort);
   localparam byte_bt MemIslNumWideBanks = 2;
   localparam shrt_bt MemIslWordsPerBank = 1024;
-  // Memory Island size = 16 * 2 * 1024 * 4 B = 128 KB
+  // WIESEP: Memory Island size = 16 * 2 * 4096 * 32 bit = 512 KB
 
   // Hyperbus
   localparam byte_bt HyperbusIdx = MemIslandIdx + 1;
-  localparam doub_bt HyperbusRegionStart = 64'h5000_0000;
-  //TODO(smazzola): Correct size of HyperRAM?
-  localparam doub_bt HyperbusRegionEnd = HyperbusRegionStart + 64'h1000_0000;
+  // WIESEP: Address space 256 MiB
+  localparam doub_bt HyperbusRegionLength = 64'h1000_0000;
+  localparam doub_bt HyperbusRegionStart = 64'h8000_0000;
+  localparam doub_bt HyperbusRegionEnd = HyperbusRegionStart + HyperbusRegionLength;
 
   localparam int unsigned HypNumPhys = 1;
   localparam int unsigned HypNumChips = 2;

hw/chimera_top_wrapper.sv

@@ -122,6 +122,10 @@ module chimera_top_wrapper
   logic [iomsb(ChsCfg.NumExtDbgHarts):0] dbg_ext_req;
   logic [iomsb(ChsCfg.NumExtDbgHarts):0] dbg_ext_unavail;
 
+  // Logic signals to APB dump mdoule
+  apb_req_t apb_to_dump_req;
+  apb_resp_t apb_from_dump_rsp;
+
   // ---------------------------------------
   // |         Cheshire SoC                |
   // ---------------------------------------
@@ -237,6 +241,15 @@ module chimera_top_wrapper
     .rst_ni   (rst_ni),
     .reg_req_i(reg_slv_req[ExtCfgRegsIdx]),
     .reg_rsp_o(reg_slv_rsp[ExtCfgRegsIdx]),
+    .apb_req_o(apb_to_dump_req),
+    .apb_rsp_i(apb_from_dump_rsp)
+  );
+
+  apb_dump_msg i_apb_dump_msg (
+    .clk_i    (soc_clk_i),
+    .rst_ni   (rst_ni),
+    .apb_rsp_o(apb_from_dump_rsp),
+    .apb_req_i(apb_to_dump_req),
     .apb_req_o(apb_req_o),
     .apb_rsp_i(apb_rsp_i)
   );

hw/clusters/chimera_cluster.sv

@@ -244,6 +244,20 @@ module chimera_cluster
   typedef logic [TcdmAddrWidth-1:0] tcdm_addr_t;
   `TCDM_TYPEDEF_ALL(tcdm_dma, tcdm_addr_t, data_dma_t, strb_dma_t, logic)
 
+  function automatic snitch_pma_pkg::rule_t [snitch_pma_pkg::NrMaxRules-1:0] get_cached_regions();
+    automatic snitch_pma_pkg::rule_t [snitch_pma_pkg::NrMaxRules-1:0] cached_regions;
+    cached_regions = '{default: '0};
+    cached_regions[0] = '{base: HyperbusRegionStart, mask: 48'hffff_1000_0000}; // Hyperbus (256 MiB)
+    cached_regions[1] = '{base: MemIslRegionStart, mask: 48'hffff_fff8_0000}; // Memory Island ( 512 KiB)
+    return cached_regions;
+  endfunction
+
+  localparam snitch_pma_pkg::snitch_pma_t SnitchPMACfg = '{
+      NrCachedRegionRules: 2,
+      CachedRegion: get_cached_regions(),
+      default: 0
+  };
+
   snitch_cluster #(
     .PhysicalAddrWidth(Cfg.ChsCfg.AddrWidth),
     .NarrowDataWidth  (ClusterDataWidth),            // SCHEREMO: Convolve needs this...
@@ -253,15 +267,19 @@ module chimera_cluster
     .NarrowUserWidth  (Cfg.ChsCfg.AxiUserWidth),
     .WideUserWidth    (Cfg.ChsCfg.AxiUserWidth),
 
-    .BootAddr        (SnitchBootROMRegionStart),
-    .IntBootromEnable(0),
+    .AliasRegionEnable(1),
+    .AliasRegionBase  ('h1800_0000),
+    .SnitchPMACfg     (SnitchPMACfg),
+    .BootAddr         (SnitchBootROMRegionStart),
+    .IntBootromEnable (0),
 
     .NrHives          (1),
     .NrCores          (NrCores),
     .TCDMDepth        (1024),
     .ZeroMemorySize   (64),
     .ClusterPeriphSize(64),
     .NrBanks          (16),
+    // WIESEP: TCDM size = 16 * 1024 * 64 bit = 128 KiB
 
     .DMANumAxInFlight(3),
     .DMAReqFifoDepth (3),

sw/include/soc_addr_map.h

@@ -34,6 +34,6 @@ static uint8_t _chimera_numCores[] = {CLUSTER_0_NUMCORES, CLUSTER_1_NUMCORES, CL
 #define FLL_BASE_ADDR 0x30003000
 
 #define HYPERBUS_CFG_BASE 0x30005000
-#define HYPERRAM_BASE 0x50000000
+#define HYPERRAM_BASE 0x80000000
 
 #endif

target/sim/vsim/run.tcl

@@ -0,0 +1,11 @@
+# Copyright 2026 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Philip wiese <wiesep@iis.ee.ethz.ch>
+
+source setup.chimera_soc.tcl
+source compile.tcl
+source start.chimera_soc.tcl
+do wave/waves.tcl
+run -a

target/sim/vsim/wave/waves.tcl

@@ -0,0 +1,67 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Add a standard set of Chimera cluster signals for a given cluster_id.
+#
+# Usage:
+#   add_chimera_cluster_waves 3
+#
+proc add_chimera_cluster_waves {cluster_id num_cores} {
+  # Base paths
+  set clu_base "/tb_chimera_soc/fix/dut/i_cluster_domain/gen_clusters\[${cluster_id}\]/gen_cluster_type/i_chimera_cluster/i_test_cluster"
+  set grp "Cluster ${cluster_id}"
+
+  # Cluster-level signals
+  add wave -noupdate -group $grp ${clu_base}/cluster_base_addr_i
+  add wave -noupdate -group $grp ${clu_base}/clk_i
+  add wave -noupdate -group $grp ${clu_base}/rst_ni
+
+  # Barrier (if present)
+  add wave -noupdate -group $grp ${clu_base}/i_snitch_barrier/barrier_i
+  add wave -noupdate -group $grp ${clu_base}/i_snitch_barrier/arrival_q
+  add wave -noupdate -group $grp ${clu_base}/i_snitch_barrier/barrier_o
+
+  # iCache/Hive signals (note: hive is commonly not per-core; keep under a subgroup)
+  # Adjust gen_hive index if needed.
+  add wave -noupdate -group $grp -group {iCache} ${clu_base}/gen_hive\[0\]/i_snitch_hive/*
+
+  # Per-core signals.
+  for {set core 0} {$core < $num_cores} {incr core} {
+    set core_base "${clu_base}/gen_core\[${core}\]/i_snitch_cc"
+    set core_grp "Core ${core}"
+
+    add wave -noupdate -group $grp -group $core_grp ${core_base}/hart_id_i
+    add wave -noupdate -group $grp -group $core_grp ${core_base}/i_snitch/pc_q
+    add wave -noupdate -group $grp -group $core_grp ${core_base}/i_snitch/wfi_q
+  }
+}
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -expand -group {Global} {/tb_chimera_soc/fix/dut/soc_clk_i}
+add wave -noupdate -expand -group {Global} {/tb_chimera_soc/fix/dut/clu_clk_i}
+add wave -noupdate -expand -group {Global} {/tb_chimera_soc/fix/dut/rtc_i}
+add wave -noupdate -expand -group {Global} {/tb_chimera_soc/fix/dut/rst_ni}
+add wave -noupdate -expand -group {Global} {/tb_chimera_soc/fix/dut/uart_tx_o}
+add wave -noupdate -expand -group {Global} {/tb_chimera_soc/fix/dut/uart_rx_i}
+
+add wave -noupdate -expand -group {CVA6} {/tb_chimera_soc/fix/dut/i_cheshire/gen_cva6_cores[0]/i_core_cva6/hart_id_i}
+add wave -noupdate -expand -group {CVA6} {/tb_chimera_soc/fix/dut/i_cheshire/gen_cva6_cores[0]/i_core_cva6/pc_commit}
+
+add wave -noupdate -expand -group {Cluster Register} {tb_chimera_soc/fix/dut/i_reg_top/reg2hw}
+
+# Add waves for Cluster 0
+add_chimera_cluster_waves 0 9
+# Add waves for Cluster 1
+add_chimera_cluster_waves 1 9
+# Add waves for Cluster 2
+add_chimera_cluster_waves 2 9
+# Add waves for Cluster 3
+add_chimera_cluster_waves 3 9
+# Add waves for Cluster 4
+add_chimera_cluster_waves 4 9
+
+# Finalize
+update