Upgrade Cheshire (64-bit CVA6)

Bender.lock

@@ -17,7 +17,7 @@ packages:
     - obi_peripherals
     - register_interface
   axi:
-    revision: 8e04779f341eb2c89412aae92223a292beef487e
+    revision: 0df61e9b7c3e7cd62bf8fb7388a3089908e71f89
     version: null
     source:
       Git: https://github.com/colluca/axi
@@ -37,8 +37,8 @@ packages:
     - register_interface
     - tech_cells_generic
   axi_riscv_atomics:
-    revision: 0ac3a78fe342c5a5b9b10bff49d58897f773059e
-    version: 0.8.2
+    revision: 97a1dd2ac643c276880420a0cf8eea697f228aa9
+    version: 0.8.3
     source:
       Git: https://github.com/pulp-platform/axi_riscv_atomics.git
     dependencies:
@@ -71,7 +71,7 @@ packages:
     - common_cells
     - register_interface
   cheshire:
-    revision: 586cb0225be5c57f5ffcf67bd490763efd9b4d24
+    revision: 7e5796c96f03819c8293ac4bb55cfcff481677f5
     version: null
     source:
       Git: https://github.com/pulp-platform/cheshire.git
@@ -87,6 +87,7 @@ packages:
     - common_cells
     - common_verification
     - cva6
+    - dram_rtl_sim
     - idma
     - irq_router
     - opentitan_peripherals
@@ -95,8 +96,8 @@ packages:
     - serial_link
     - unbent
   clic:
-    revision: 8ed76ffc779a435d0ed034f3068e4c3334fe2ecf
-    version: 2.0.0
+    revision: 6515a71eb4ae3b143ab912d265e79832b3179a76
+    version: 3.0.0
     source:
       Git: https://github.com/pulp-platform/clic.git
     dependencies:
@@ -128,8 +129,8 @@ packages:
     dependencies:
     - common_cells
   common_cells:
-    revision: 9afda9abb565971649c2aa0985639c096f351171
-    version: 1.38.0
+    revision: 9ca8a7655f741e7dd5736669a20a301325194c28
+    version: 1.39.0
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
@@ -142,17 +143,24 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   cva6:
-    revision: 630bd959c9cc69a35d461a2abc205310d2edacf8
+    revision: 4c02b24fe7c04690f626776a92274da24f80d1da
     version: null
     source:
-      Git: https://github.com/Scheremo/cva6.git
+      Git: https://github.com/pulp-platform/cva6.git
     dependencies:
     - axi
     - common_cells
     - fpnew
     - tech_cells_generic
+  dram_rtl_sim:
+    revision: 2cac4a9e12a60537567276b539ab6c919c87b5dc
+    version: 0.1.1
+    source:
+      Git: https://github.com/pulp-platform/dram_rtl_sim.git
+    dependencies:
+    - axi
   fpnew:
-    revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315
+    revision: e5aa6a01b5bbe1675c3aa8872e1203413ded83d1
     version: null
     source:
       Git: https://github.com/pulp-platform/cvfpu.git
@@ -167,8 +175,8 @@ packages:
     dependencies:
     - common_cells
   hyperbus:
-    revision: 841deb9d821b63bf05a1c85d3a4746352a8bcae2
-    version: null
+    revision: 2a14bd8f9a985b488ee23d240764f52f129f7729
+    version: 0.0.9
     source:
       Git: https://github.com/pulp-platform/hyperbus.git
     dependencies:
@@ -198,7 +206,7 @@ packages:
     - common_cells
     - register_interface
   memory_island:
-    revision: 64828cb7a9ccc1f1656ec92d06129072f445c319
+    revision: d072ba0945adad5ccd0af2d4604abe57c1058252
     version: null
     source:
       Git: https://github.com/pulp-platform/memory_island.git
@@ -234,8 +242,8 @@ packages:
     - register_interface
     - tech_cells_generic
   register_interface:
-    revision: 8e8c209ea559d3b54f45cf30fcce95ce70ff5e49
-    version: 0.4.6
+    revision: d6e1d4cdaab7870f4faf3f88a1c788eaf5ac129d
+    version: 0.4.7
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:
@@ -252,8 +260,8 @@ packages:
     - common_cells
     - tech_cells_generic
   scm:
-    revision: 472f99affe44ff7b282b519c047a3cfeb35b16c6
-    version: 1.2.0
+    revision: 1976c7efb4979271eee2abe262fde0f9a20e2557
+    version: 1.2.1
     source:
       Git: https://github.com/pulp-platform/scm.git
     dependencies:

Bender.yml

@@ -9,25 +9,20 @@ package:
     - "Lorenzo Leone <lleone@iis.ee.ethz.ch>"
 
 dependencies:
-  register_interface:       { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3  }
-  axi:                      { git: https://github.com/colluca/axi,                            rev: multicast }
-  cheshire:                 { git: "https://github.com/pulp-platform/cheshire.git",           rev: 586cb0225be5c57f5ffcf67bd490763efd9b4d24}
-  snitch_cluster:           { git: "https://github.com/pulp-platform/snitch_cluster.git",     rev: 5b2fccd96c42812774c20ab2f9b811e164809789}
-  common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.31.1}
+  register_interface:       { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.7 }
+  axi:                      { git: "https://github.com/colluca/axi",                          rev: 0df61e9b7c3e7cd62bf8fb7388a3089908e71f89 } # multicast branch
+  cheshire:                 { git: "https://github.com/pulp-platform/cheshire.git",           rev: 7e5796c96f03819c8293ac4bb55cfcff481677f5 } # wiesep/chimera-pulp-v2.0.0 branch
+  snitch_cluster:           { git: "https://github.com/pulp-platform/snitch_cluster.git",     rev: 5b2fccd96c42812774c20ab2f9b811e164809789 } # main branch
+  common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.39.0 }
   idma:                     { git: "https://github.com/pulp-platform/iDMA.git",               version: 0.6.5 }
-  memory_island:            { git: "https://github.com/pulp-platform/memory_island.git",      rev: 64828cb7a9ccc1f1656ec92d06129072f445c319 } # main branch
-  apb:                      { git: "https://github.com/pulp-platform/apb.git",                version: 0.2.4          }
-  hyperbus:                 { git: "https://github.com/pulp-platform/hyperbus.git",           rev: aottaviano/nonfree } # TMP: to fix hyperbus model issue
+  memory_island:            { git: "https://github.com/pulp-platform/memory_island.git",      rev: d072ba0945adad5ccd0af2d4604abe57c1058252 } # main branch
+  apb:                      { git: "https://github.com/pulp-platform/apb.git",                version: 0.2.4 }
+  hyperbus:                 { git: "https://github.com/pulp-platform/hyperbus.git",           rev: 2a14bd8f9a985b488ee23d240764f52f129f7729 } # aottaviano/nonfree branch
   tech_cells_generic:       { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.12 }
 
 export_include_dirs:
   - hw/include
 
-workspace:
-  package_links:
-    cheshire: cheshire
-    idma: idma
-
 sources:
   # Level 0
   - hw/chimera_pkg.sv

Makefile

@@ -35,7 +35,7 @@ SN_CFG = $(SN_ROOT)/cfg/default.json
 BENDER_YML = $(CHIM_ROOT)/Bender.yml
 BENDER_LOCK = $(CHIM_ROOT)/Bender.lock
 
-CHS_XLEN ?= 32
+CHS_XLEN ?= 64
 
 CHIM_HW_DIR ?= $(CHIM_ROOT)/hw
 CHIM_SW_DIR ?= $(CHIM_ROOT)/sw

bender.mk

@@ -6,6 +6,6 @@
 # Lorenzo Leone <lleone@iis.ee.ethz.ch>
 
 COMMON_TARGS ?=
-COMMON_TARGS += -t snitch_cluster -t cv32a6_convolve -t cva6 -t rtl
+COMMON_TARGS += -t snitch_cluster -t cv64a6_imafdchsclic_sv39_wb -t cva6 -t rtl
 
 SIM_TARGS = $(COMMON_TARGS) -t test -t sim

hw/chimera_pkg.sv

@@ -174,13 +174,15 @@ ExtClusters
 
     cfg.Vga = 0;
     cfg.SerialLink = 0;
+    cfg.Clic = 1;
+    cfg.Usb = 0;
     // SCHEREMO: Fully remove LLC
     cfg.LlcNotBypass = 0;
     cfg.LlcOutConnect = 0;
 
     // AXI CFG
     cfg.AxiMstIdWidth = 2;
-    cfg.AxiDataWidth = 32;
+    cfg.AxiDataWidth = 64;
     cfg.AddrWidth = 48;
     cfg.LlcOutRegionEnd = 'hFFFF_FFFF;
 

iis-env.sh

@@ -9,7 +9,8 @@ export VOPT="questa-2022.3 vopt"
 export VLIB="questa-2022.3 vlib"
 export BASE_PYTHON=/usr/local/anaconda3/bin/python3.11
 export CHS_SW_32_GCC_BINROOT=/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0/bin
-export RISCV_GCC_BINROOT=/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0/bin
+export CHS_SW_64_GCC_BINROOT=/usr/pack/riscv-1.0-kgf/riscv64-gcc-12.2.0/bin
+export CHS_SW_GCC_BINROOT=/usr/pack/riscv-1.0-kgf/riscv64-gcc-12.2.0/bin
 export CC=/usr/pack/gcc-11.2.0-af/linux-x64/bin/gcc
 export CXX=/usr/pack/gcc-11.2.0-af/linux-x64/bin/g++
 export CMAKE=cmake-3.28.3

sw/sw.mk

@@ -14,8 +14,8 @@ CHS_SW_INCLUDES += -I$(CHIM_SW_DIR)/include
 
 # SCHEREMO: use im for platform-level SW, as the smallest common denominator between CVA6 and the Snitch cluster.
 # CVA6's bootrom however needs imc, so override that for this specific case.
-CHS_SW_FLAGS += -falign-functions=64 -march=rv32im
-CHS_BROM_FLAGS += -march=rv32imc
+CHS_SW_FLAGS += -falign-functions=64 -march=rv64gc_zifencei -mabi=lp64d
+CHS_BROM_FLAGS += -march=rv64gc_zifencei -mabi=lp64d
 
 CHS_SW_LDFLAGS += -L$(CHIM_SW_DIR)/lib
 

sw/tests/testHyperbusAddr.c

@@ -15,11 +15,15 @@
 
 int main() {
     volatile uint8_t *regPtr = (volatile uint8_t *)SOC_CTRL_BASE;
-    setAllClusterReset(regPtr, 0);
-    setAllClusterClockGating(regPtr, 0);
+    // setAllClusterReset(regPtr, 0);
+    // setAllClusterClockGating(regPtr, 0);
+    volatile uint32_t *hyperCtrlPtr = (volatile uint32_t *)HYPERBUS_CFG_BASE;
     volatile uint32_t *hyperMemPtr = (volatile uint32_t *)HYPER_BASE;
     volatile uint32_t result;
 
+    // Write T_TX_CLK values
+    hyperCtrlPtr[5] = 4;
+
     // write
     *(hyperMemPtr) = TESTVAL;
     // read

target/sim/src/tb_chimera_soc.sv

@@ -41,7 +41,7 @@ module tb_chimera_soc
     force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_req_i[1] = 1'b1;
     force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_we_i[1] = 1'b1;
     force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_wdata_i[1] = write_data;
-    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_strb_i[1] = 4'hf;
+    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_strb_i[1] = 8'hff;
     force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_gnt_o[1] = 1'b0;
     force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_rvalid_o[1] = 1'b0;
   endtask
@@ -58,18 +58,19 @@ module tb_chimera_soc
       $display("[FAST PRELOAD] Preloading section at 0x%h (%0d bytes)", sec_addr, sec_len);
       if (read_section(sec_addr, bf, sec_len))
         $fatal(1, "[FAST PRELOAD] Failed to read ELF section!");
-      @(posedge fix.vip.soc_clk);  // 
+      @(posedge fix.vip.soc_clk);  //
       for (longint i = 0; i <= sec_len; i += riscv::XLEN / 8) begin
         bit checkpoint = (i != 0 && i % 512 == 0);
-        if (checkpoint)
+        //if (checkpoint)
           $display(
-              "[FAST PRELOAD] - %0d/%0d bytes (%0d%%)",
+              "%0t ns [FAST PRELOAD] - %0d/%0d bytes (%0d%%)",
+              $time,
               i,
               sec_len,
               i * 100 / (sec_len > 1 ? sec_len - 1 : 1)
           );
         @(posedge fix.vip.soc_clk);
-        force_write((sec_addr + i), {bf[i+3], bf[i+2], bf[i+1], bf[i]});
+        force_write((sec_addr + i), {bf[i+7], bf[i+6], bf[i+5], bf[i+4], bf[i+3], bf[i+2], bf[i+1], bf[i]});
       end
     end
     @(posedge fix.vip.soc_clk);
@@ -112,7 +113,7 @@ module tb_chimera_soc
           fix.vip.uart_debug_elf_run_and_wait(preload_elf, exit_code);
         end
         3: begin  // FAST DEBUG
-          // Initialize JTAG 
+          // Initialize JTAG
           fix.vip.jtag_init();
           // Halt the core
           fix.vip.jtag_halt_hart();