pulp-platform · ezelioli · Nov 17, 2025 · Nov 17, 2025 · Nov 27, 2025 · Nov 27, 2025
diff --git a/.github/workflows/full-flow.yml b/.github/workflows/full-flow.yml
@@ -31,7 +31,7 @@ jobs:
       - name: Run Yosys, OpenROAD and KLayout
         uses: ./.github/actions/oseda-cmd
         with:
-          cmd: "make yosys && make openroad && make klayout"
+          cmd: "cd yosys && ./run.sh && cd ../openroad && ./run.sh && cd ../klayout && ./def2gds.sh"
       - name: Upload openroad outputs
         uses: actions/upload-artifact@v4
         with:

diff --git a/.github/workflows/short-flow.yml b/.github/workflows/short-flow.yml
@@ -25,7 +25,7 @@ jobs:
       - name: Run simulation commands in OSEDA
         uses: ./.github/actions/oseda-cmd
         with:
-          cmd: "make sw && make verilator"
+          cmd: "make sw && cd verilator && ./run.sh"
       - name: Upload built software
         uses: actions/upload-artifact@v4
         with:
@@ -57,7 +57,7 @@ jobs:
       - name: Setup OSEDA container
         uses: ./.github/actions/oseda-cmd
         with:
-          cmd: "make yosys && tail -n 40 yosys/reports/*area.rpt"
+          cmd: "cd yosys && ./run.sh && tail -n 40 reports/*area.rpt"
       - name: Upload synthesis outputs
         uses: actions/upload-artifact@v4
         with:

diff --git a/Makefile b/Makefile
@@ -4,170 +4,78 @@
 #
 # Authors:
 # - Philippe Sauter <phsauter@iis.ee.ethz.ch>
-
-# Tools
-BENDER	  ?= bender
-PYTHON3   ?= python3
-VERILATOR ?= /foss/tools/bin/verilator
-YOSYS     ?= yosys
-OPENROAD  ?= openroad
-KLAYOUT   ?= klayout
-VSIM      ?= vsim
+# - Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
 
 # Directories
 # directory of the path to the last called Makefile (this one)
-PROJ_DIR  := $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST)))))
-
-
-default: help
-
-################
-# Dependencies #
-################
-# Download RCX file used for parasitic extraction from ORFS (configuration got ok by IHP)
-IHP_RCX_URL  := "https://raw.githubusercontent.com/The-OpenROAD-Project/OpenROAD-flow-scripts/7747f88f70daaeb63f43ce36e71829707b7e3fa7/flow/platforms/ihp-sg13g2/IHP_rcx_patterns.rules"
-IHP_RCX_FILE := $(PROJ_DIR)/openroad/IHP_rcx_patterns.rules
-
-## Checkout/update dependencies using Bender
-checkout: $(IHP_RCX_FILE)
-	$(BENDER) checkout
-	git submodule update --init --recursive
-
-$(IHP_RCX_FILE): 
-	curl -L -o $@ $(IHP_RCX_URL)
-
-## Reset dependencies (without updating Bender.lock)
-clean-deps:
-	rm -rf .bender
-	git submodule deinit -f --all
-
-.PHONY: checkout clean-deps
-
-
-############
-# Software #
-############
-SW_HEX ?= sw/bin/helloworld.hex
-
-$(SW_HEX): sw/*.c sw/*.h sw/*.S sw/*.ld
-	$(MAKE) -C sw/ compile
+PROJ_DIR := $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST)))))
+SW_DIR   := $(PROJ_DIR)/sw
+SRC_DIR  := $(SW_DIR)/lib/src
+INC_DIR  := $(SW_DIR)/lib/inc
+BIN_DIR  := $(SW_DIR)/bin
+
+# Toolchain
+RISCV_PREFIX  ?= riscv64-unknown-elf-
+RISCV_CC      := $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP := $(RISCV_PREFIX)objdump
+RISCV_OBJCOPY := $(RISCV_PREFIX)objcopy
+RISCV_LD      := $(RISCV_PREFIX)ld
+
+# Compilation and linking flags
+RISCV_FLAGS   := -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding
+RISCV_CCFLAGS := $(RISCV_FLAGS) -I$(INC_DIR) -I$(SW_DIR)
+RISCV_LDFLAGS := $(RISCV_FLAGS) -static -nostartfiles -lm -lgcc
+
+# Build files
+CRT0        := $(SW_DIR)/crt0.S
+LINK        := $(SW_DIR)/link.ld
+LIB_SOURCES := $(wildcard $(SRC_DIR)/*.[cS])
+LIB_OBJS    := $(LIB_SOURCES:$(SRC_DIR)/%=$(SRC_DIR)/%.o)
+
+# Build all assembly and C files in the top level as seperate binaries
+TOP_SOURCES   := $(filter-out $(CRT0), $(wildcard $(SW_DIR)/*.[cS]))
+TOP_BASENAMES := $(basename $(notdir $(TOP_SOURCES)))
+ALL_TARGETS   := $(TOP_BASENAMES:%=$(BIN_DIR)/%.dump) $(TOP_BASENAMES:%=$(BIN_DIR)/%.hex)
+
+# Default make target
+.PHONY: default
+default: all
+
+# Create output bin directory
+$(BIN_DIR):
+	mkdir -p $(BIN_DIR)
+
+# Compile assembly file
+%.S.o: %.S
+	$(RISCV_CC) $(RISCV_CCFLAGS) -c $< -o $@
+
+# Compile C file
+%.c.o: %.c
+	$(RISCV_CC) $(RISCV_CCFLAGS) -c $< -o $@
+
+# Link assembly application
+$(BIN_DIR)/%.elf: $(SW_DIR)/%.S.o $(CRT0).o $(LIB_OBJS) | $(BIN_DIR)
+	$(RISCV_CC) -o $@ $^ $(RISCV_LDFLAGS) -T$(LINK)
+
+# Link C application
+$(BIN_DIR)/%.elf: $(SW_DIR)/%.c.o $(CRT0).o $(LIB_OBJS) | $(BIN_DIR)
+	$(RISCV_CC) -o $@ $^ $(RISCV_LDFLAGS) -T$(LINK)
+
+# Create dis-assembled version of ELF binary
+$(BIN_DIR)/%.dump: $(BIN_DIR)/%.elf
+	$(RISCV_OBJDUMP) -D -s $< >$@
+
+# Create hex version of ELF binary
+$(BIN_DIR)/%.hex: $(BIN_DIR)/%.elf
+	$(RISCV_OBJCOPY) -O verilog $< $@
 
 ## Build all top-level programs in sw/
-software: $(SW_HEX)
-
-sw: $(SW_HEX)
-
-.PHONY: software sw
-
-##################
-# RTL Simulation #
-##################
-# Questasim/Modelsim/vsim
-VLOG_ARGS  = -svinputport=compat
-VSIM_ARGS  = -t 1ns -voptargs=+acc
-VSIM_ARGS += -suppress vsim-3009 -suppress vsim-8683 -suppress vsim-8386
-
-vsim/compile_rtl.tcl: Bender.lock Bender.yml
-	$(BENDER) script vsim -t rtl -t vsim -t simulation -t verilator -DSYNTHESIS -DSIMULATION  --vlog-arg="$(VLOG_ARGS)" > $@
-
-vsim/compile_netlist.tcl: Bender.lock Bender.yml
-	$(BENDER) script vsim -t ihp13 -t vsim -t simulation -t verilator -t netlist_yosys -DSYNTHESIS -DSIMULATION > $@
-
-## Simulate RTL using Questasim/Modelsim/vsim
-vsim: vsim/compile_rtl.tcl $(SW_HEX)
-	rm -rf vsim/work
-	cd vsim; $(VSIM) -c -do "source compile_rtl.tcl; exit"
-	cd vsim; $(VSIM) +binary="$(realpath $(SW_HEX))" -gui tb_croc_soc $(VSIM_ARGS)
-
-## Simulate netlist using Questasim/Modelsim/vsim
-vsim-yosys: vsim/compile_netlist.tcl $(SW_HEX) yosys/out/croc_chip_yosys_debug.v
-	rm -rf vsim/work
-	cd vsim; $(VSIM) -c -do "source compile_netlist.tcl; source compile_tech.tcl; exit"
-	cd vsim; $(VSIM) -gui tb_croc_soc $(VSIM_ARGS)
-
-
-# Verilator
-# Turn off style warnings and well-defined SystemVerilog warnings that should be part of -Wno-style
-VERILATOR_ARGS = -Wno-fatal -Wno-style \
-	-Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE
-
-VERILATOR_ARGS += --binary -j 0
-VERILATOR_ARGS += --timing --autoflush --trace-fst --trace-threads 2 --trace-structs
-VERILATOR_ARGS +=  --unroll-count 1 --unroll-stmts 1
-VERILATOR_ARGS += --x-assign fast --x-initial fast
-VERILATOR_CFLAGS += -O3 -march=native -mtune=native
-
-verilator/croc.f: Bender.lock Bender.yml
-	$(BENDER) script verilator -t rtl -t verilator -t cve2_include_tracer -DSYNTHESIS -DVERILATOR -DTRACE_EXECUTION > $@
-
-verilator/obj_dir/Vtb_croc_soc: verilator/croc.f $(SW_HEX)
-	cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -O3 --top tb_croc_soc -f croc.f
-
-## Simulate RTL using Verilator
-verilator: verilator/obj_dir/Vtb_croc_soc
-	cd verilator; obj_dir/Vtb_croc_soc +binary="$(realpath $(SW_HEX))" | tee croc.log
-
-.PHONY: verilator vsim vsim-yosys
-
-
-####################
-# Open Source Flow #
-####################
-# Bender manages the different IPs and can be used to generate file-lists for synthesis
-TOP_DESIGN     ?= croc_chip
-DUT_DESIGN	   ?= croc_soc
-BENDER_TARGETS ?= asic ihp13 rtl synthesis
-SV_DEFINES     ?= VERILATOR SYNTHESIS COMMON_CELLS_ASSERTS_OFF
-
-## Generate croc.flist used to read design in yosys
-yosys-flist: Bender.lock Bender.yml rtl/*/Bender.yml
-	$(BENDER) script flist-plus $(foreach t,$(BENDER_TARGETS),-t $(t)) $(foreach d,$(SV_DEFINES),-D $(d)=1) > $(PROJ_DIR)/croc.flist
-
-include yosys/yosys.mk
-include openroad/openroad.mk
-
-klayout/croc_chip.gds: $(OR_OUT)/croc.def klayout/*.sh klayout/*.py
-	./klayout/def2gds.sh
-
-## Generate merged .gds from openroads .def output
-klayout: klayout/croc_chip.gds
-
-.PHONY: klayout yosys-flist
-
-
-#################
-# Documentation #
-#################
-
-help: Makefile
-	@printf "Available targets:\n------------------\n"
-	@for mkfile in $(MAKEFILE_LIST); do \
-		awk '/^[a-zA-Z\-\_0-9]+:/ { \
-			helpMessage = match(lastLine, /^## (.*)/); \
-			if (helpMessage) { \
-				helpCommand = substr($$1, 0, index($$1, ":")-1); \
-				helpMessage = substr(lastLine, RSTART + 3, RLENGTH); \
-				printf "%-20s %s\n", helpCommand, helpMessage; \
-			} \
-		} \
-		{ lastLine = $$0 }' $$mkfile; \
-	done
-
-.PHONY: help
-
-
-###########
-# Cleanup #
-###########
+.PHONY: all
+all: $(ALL_TARGETS)
 
 ## Delete generated files and directories
-clean: 
-	rm -f $(SV_FLIST)
-	rm -f klayout/croc_chip.gds
-	rm -rf verilator/obj_dir/
-	rm -f verilator/croc.f
-	rm -f verilator/croc.vcd
-	$(MAKE) ys_clean
-	$(MAKE) or_clean
-
 .PHONY: clean
+clean:
+	rm -rf $(BIN_DIR)
+	rm -f $(PROJ_DIR)/sw/*.o
+	rm -f $(PROJ_DIR)/sw/lib/src/*.o
diff --git a/openroad/openroad.mk b/openroad/openroad.mk
diff --git a/openroad/run.sh b/openroad/run.sh
@@ -0,0 +1,18 @@
+#!/bin/bash
+
+# Set variables
+OPENROAD=${OPENROAD:-openroad}
+QT_QPA_PLATFORM=${QT_QPA_PLATFORM:-"offscreen"}
+
+# Clean up generated files
+[ -f croc.log ] && rm croc.log
+rm -rf reports/
+rm -rf out/
+rm -rf save/
+mkdir reports
+mkdir out
+mkdir save
+
+# Run OpenRoad
+QT_QPA_PLATFORM="offscreen" ${OPENROAD} scripts/chip.tcl -log croc.log 2>&1 | TZ=UTC gawk '{ print strftime("[%Y-%m-%d %H:%M %Z]"), $0 }'
+
diff --git a/openroad/scripts/chip.tcl b/openroad/scripts/chip.tcl
@@ -8,23 +8,14 @@
 # - Philippe Sauter   <phsauter@iis.ee.ethz.ch>
 
 # The main OpenRoad chip flow
-set proj_name $::env(PROJ_NAME)
-set netlist $::env(NETLIST)
-set top_design $::env(TOP_DESIGN)
-set report_dir $::env(REPORTS)
-set save_dir $::env(SAVE)
-set time [elapsed_run_time]
-set step_by_step_debug 0
-
-# helper scripts
-source scripts/reports.tcl
-source scripts/checkpoint.tcl
-
-# initialize technology data
-source scripts/init_tech.tcl
 
+# Helper variables
 set log_id 0
+set step_by_step_debug 0
+set time [elapsed_run_time]
 
+# Define variables, helper functions and initialize technology data
+source scripts/startup.tcl
 
 ###############################################################################
 # Initialization                                                              #