Introduce verification framework, regression testing, GitHub/GitLab CI, and fractional-priority arbiter

.github/workflows/gitlab-ci.yml

@@ -0,0 +1,29 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Author: Paul Scheffler <paulsc@iis.ee.ethz.ch>
+
+name: gitlab-ci
+
+on: [ push, pull_request, workflow_dispatch ]
+
+permissions:
+  # deployments permission to deploy GitHub pages website
+  deployments: write
+  # contents permission to update benchmark contents in gh-pages branch
+  contents: write
+
+jobs:
+  gitlab-ci:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Check Gitlab CI
+        uses: pulp-platform/pulp-actions/gitlab-ci@v1
+        # Skip on forks or pull requests from forks due to missing secrets.
+        if: github.repository == 'pulp-platform/hci' && (github.event_name != 'pull_request' || github.event.pull_request.head.repo.full_name == github.repository)
+        with:
+          domain: iis-git.ee.ethz.ch
+          repo: github-mirror/hci
+          token: ${{ secrets.GITLAB_TOKEN }}
+

.gitignore

@@ -9,3 +9,4 @@ target/verif/vsim/compile.tcl
 target/verif/vsim/modelsim.ini
 target/verif/vsim/transcript
 target/verif/vsim/vsim.wlf
+target/verif/exploration/results

.gitlab-ci.yml

@@ -0,0 +1,44 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Paul Scheffler <paulsc@iis.ee.ethz.ch>
+
+# We initialize the nonfree repo, then spawn a sub-pipeline from it
+
+variables:
+  GIT_SUBMODULE_STRATEGY: recursive
+  # Our reference GCC toolchain for reproducible builds
+
+before_script:
+  - python -V  # Print out python version for debugging
+  - python -m pip install --user virtualenv
+
+.base:
+  artifacts:
+    when: always
+    expire_in: 1 week
+
+stages:
+  - build
+  - test
+
+build:
+  stage: build
+  script:
+    - make checkout
+  artifacts:
+    when: always
+    expire_in: 3 hours
+    paths: [ .bender ]
+
+testset:
+  extends: .base
+  needs: [ build ]
+  stage: test
+  script:
+    - regr/full_regression.sh
+  artifacts:
+    when: always
+    expire_in: 1 year
+    paths: [ regr/hci_tests.xml ]

Bender.yml

@@ -2,10 +2,11 @@ package:
   name: hci
   authors:
     - "Francesco Conti <f.conti@unibo.it>"
-    - "Gianna Paulin <pauling@iis.ee.ethz.ch"
+    - "Gianna Paulin <pauling@iis.ee.ethz.ch>"
     - "Tobias Riedener <tobiasri@student.ethz.ch>"
     - "Luigi Ghionda <luigi.ghionda2@studio.it>"
     - "Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>"
+    - "Sergio Mazzola <smazzola@iis.ee.ethz.ch>"
 
 dependencies:
   hwpe-stream:            { git: "https://github.com/pulp-platform/hwpe-stream.git", version: 1.9.0 }
@@ -70,8 +71,8 @@ sources:
           # Level 1
           - target/verif/src/application_driver.sv
           - target/verif/src/tcdm_banks_wrap.sv
-          - target/verif/src/latency_monitor.sv
-          - target/verif/src/throughput_monitor.sv
+          - target/verif/src/req_gnt_monitor.sv
+          - target/verif/src/bandwidth_monitor.sv
           # Level 2
           - target/verif/src/simulation_report.sv
           # Level 3

README.md

@@ -8,6 +8,38 @@ The `hci` repository contains the definition of the Heterogeneous Cluster Interc
  - https://github.com/pulp-platform/neureka
  - https://github.com/pulp-platform/redmule
 
+# Verification flow
+The typical full flow is:
+
+```
+make checkout       # Fetch and check out dependencies via Bender
+make config-verif   # Generate Makefiles from JSON verification configs
+make stim-verif     # Generate simulation stimulus vectors (requires Python 3)
+make compile-verif  # Compile RTL and testbench with QuestaSim
+make opt-verif      # Optimize the compiled design with vopt
+make run-verif      # Run the simulation (batch mode by default)
+```
+
+To open the simulation in the QuestaSim GUI with waveforms, pass `GUI=1`:
+
+```
+make run-verif GUI=1
+```
+
+Cleanup targets:
+
+| Target               | Effect                                             |
+|----------------------|----------------------------------------------------|
+| `clean-config-verif` | Remove generated configuration Makefiles           |
+| `clean-stim-verif`   | Remove generated stimulus vectors                  |
+| `clean-sim-verif`    | Remove QuestaSim build artifacts (work lib, logs)  |
+| `clean-verif`        | Run all three clean targets above                  |
+
+**Notes:**
+- On IIS machines, defaults to QuestaSim (`questa-2022.3`) (can be overriden with `SIM_QUESTA=<version>`). On non-IIS machines, defaults to QuestaSim available in `PATH`.
+- Verification configuration is driven by JSON files under `target/verif/config/`. Edit those before running `config-verif` and `stim-verif`.
+- `run-verif` depends on `opt-verif` and `stim-verif`, so after `checkout` and `config-verif` you can jump straight to it.
+
 # Style guide
 These IPs use a slightly different style than other PULP IPs. Refer to `STYLE.md` for some indications.
 

bender.mk

@@ -1,4 +1,4 @@
-# Copyright 2025 ETH Zurich and University of Bologna.
+# Copyright 2026 ETH Zurich and University of Bologna.
 # Solderpad Hardware License, Version 0.51, see LICENSE.solderpad for details.
 # SPDX-License-Identifier: SHL-0.51
 #

regr/basic.yml

@@ -0,0 +1,31 @@
+# Copyright (C) 2024 ETH Zurich and University of Bologna
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Author: Francesco Conti (f.conti@unibo.it)
+#
+
+hci_tests:
+  log_fair:
+    path: .
+    command: make clean-config-verif clean-stim-verif clean-sim-verif config-verif stim-verif compile-verif run-verif TESTBENCH_JSON=regr/testbench/fair/testbench.json HARDWARE_JSON=regr/hardware/log/hardware.json
+  hci_fair:
+    path: .
+    command: make clean-config-verif clean-stim-verif clean-sim-verif config-verif stim-verif compile-verif run-verif TESTBENCH_JSON=regr/testbench/fair/testbench.json HARDWARE_JSON=regr/hardware/hci/hardware.json
+  hci_hwpe_prio:
+    path: .
+    command: make clean-config-verif clean-stim-verif clean-sim-verif config-verif stim-verif compile-verif run-verif TESTBENCH_JSON=regr/testbench/hwpe_prio/testbench.json HARDWARE_JSON=regr/hardware/hci/hardware.json
+  hci_log_prio:
+    path: .
+    command: make clean-config-verif clean-stim-verif clean-sim-verif config-verif stim-verif compile-verif run-verif TESTBENCH_JSON=regr/testbench/log_prio/testbench.json HARDWARE_JSON=regr/hardware/hci/hardware.json