Fix sending of AWs for decouple_rw without decouple_aw

jobs/backend_rw_axi/simple.txt

@@ -1,4 +1,4 @@
-2
+100
 0x0
 0x3ff
 0
@@ -8,3 +8,13 @@
 0
 0
 0
+100
+0x4000
+0x43ff
+0
+0
+256
+4
+0
+1
+0

src/backend/idma_axi_write.sv

@@ -68,6 +68,10 @@ module idma_axi_write #(
     /// AXI4+ATOP write manager port response
     input  write_rsp_t write_rsp_i,
 
+    output logic w_chan_valid_o,
+    output logic w_chan_ready_o,
+    output logic w_chan_first_o,
+
     /// Data from buffer
     input  byte_t [StrbWidth-1:0] buffer_out_i,
     /// Valid from buffer
@@ -256,6 +260,10 @@ module idma_axi_write #(
         end
     end
 
+    // Channel management signals
+    assign w_chan_valid_o = write_req_o.w_valid;
+    assign w_chan_ready_o = write_rsp_i.w_ready;
+    assign w_chan_first_o = first_w;
 
     //--------------------------------------
     // Write response

src/backend/idma_axil_write.sv

@@ -61,6 +61,10 @@ module idma_axil_write #(
     /// AXI Lite write manager port response
     input  write_rsp_t write_rsp_i,
 
+    output logic w_chan_valid_o,
+    output logic w_chan_ready_o,
+    output logic w_chan_first_o,
+
     /// Data from buffer
     input  byte_t [StrbWidth-1:0] buffer_out_i,
     /// Valid from buffer
@@ -161,6 +165,11 @@ module idma_axil_write #(
     // we are ready for the next transfer internally, once the w last signal is applied
     assign w_dp_ready_o = write_happening;
 
+    // Channel management signals
+    assign w_chan_valid_o = write_req_o.w_valid;
+    assign w_chan_ready_o = write_rsp_i.w_ready;
+    assign w_chan_first_o = 1'b1; // always first, no bursting
+
     //--------------------------------------
     // Write response
     //--------------------------------------

src/backend/idma_axis_write.sv

@@ -66,6 +66,10 @@ module idma_axis_write #(
     /// AXI Stream write manager port response
     input  write_rsp_t write_rsp_i,
 
+    output logic w_chan_valid_o,
+    output logic w_chan_ready_o,
+    output logic w_chan_first_o,
+
     /// Data from buffer
     input  byte_t [StrbWidth-1:0] buffer_out_i,
     /// Valid from buffer
@@ -152,6 +156,10 @@ module idma_axis_write #(
     assign w_dp_req_ready_o = write_happening;
     assign aw_ready_o       = write_happening;
 
+    assign w_chan_valid_o   = write_req_o.tvalid;
+    assign w_chan_ready_o   = write_rsp_i.tready;
+    assign w_chan_first_o   = 1'b1; // always first, no AW channel
+
     //--------------------------------------
     // Write response
     //--------------------------------------

src/backend/idma_channel_coupler.sv

@@ -31,14 +31,12 @@ module idma_channel_coupler #(
     /// Testmode in
     input  logic testmode_i,
 
-    /// R response valid
-    input  logic r_rsp_valid_i,
-    /// R response ready
-    input  logic r_rsp_ready_i,
-    /// First R response
-    input  logic r_rsp_first_i,
-    /// Did the read originate from a decoupled request
-    input  logic r_decouple_aw_i,
+    /// W request valid
+    input  logic w_req_valid_i,
+    /// W request ready
+    input  logic w_req_ready_i,
+    /// First W request
+    input  logic w_req_first_i,
     /// Is the `AW` in the queue a decoupled request?
     input  logic aw_decouple_aw_i,
 
@@ -86,9 +84,13 @@ module idma_channel_coupler #(
 
     // counter to keep track of AR to send
     cnt_t aw_to_send_d, aw_to_send_q;
+    cnt_t aw_to_stall_d, aw_to_stall_q;
 
-    // first signal -> an R has arrived that needs to free an AW
-    assign first = r_rsp_valid_i & r_rsp_ready_i & r_rsp_first_i & !r_decouple_aw_i;
+    logic aw_stall_d, aw_stall_q;
+
+    // first signal -> a W has data that needs to free an AW
+    assign first = w_req_valid_i & w_req_first_i & ~aw_stall_q;
+    assign aw_stall_d = w_req_valid_i & ~w_req_ready_i;
 
     // stream fifo to hold AWs back
     stream_fifo_optimal_wrap #(
@@ -132,34 +134,48 @@ module idma_channel_coupler #(
 
         // defaults
         aw_to_send_d = aw_to_send_q;
+        aw_to_stall_d = aw_to_stall_q;
 
         // if we bypass the logic
         aw_sent = aw_decoupled_head & aw_valid;
-
-        // first is asserted and aw is ready -> just send AW out
-        // without changing the credit counter value
-        if (aw_ready_decoupled & first) begin
-            aw_sent = 1'b1;
-        end
-
-        // if first is asserted and aw is not ready -> increment
-        // credit counter
-        else if (!aw_ready_decoupled & first) begin
-            aw_to_send_d = aw_to_send_q + 1;
+        // if the AW is decoupled, we need to keep track of the sent AWs
+        if (aw_decoupled_head & aw_valid & aw_to_send_q == '0) begin
+            aw_to_stall_d = aw_to_stall_q + 1;
+            if (aw_ready_decoupled & first) begin
+                aw_to_stall_d = aw_to_stall_q;
+            end
         end
 
-        // if not first, aw is ready and we have credit -> count down
-        else if (aw_ready_decoupled & !first & aw_to_send_q != '0) begin
-            aw_sent = 1'b1;
-            aw_to_send_d = aw_to_send_q - 1;
+        if (aw_to_stall_q != '0) begin
+            if (first && !(aw_decoupled_head & aw_valid)) begin
+                aw_to_stall_d = aw_to_stall_q - 1;
+            end
+        end else begin
+            // first is asserted and aw is ready -> just send AW out
+            // without changing the credit counter value
+            if (aw_ready_decoupled & first) begin
+                aw_sent = 1'b1;
+            end
+
+            // if first is asserted and aw is not ready -> increment
+            // credit counter
+            else if (!aw_ready_decoupled & first) begin
+                aw_to_send_d = aw_to_send_q + 1;
+            end
+
+            // if not first, aw is ready and we have credit -> count down
+            else if (aw_ready_decoupled & !first & aw_to_send_q != '0) begin
+                aw_sent = 1'b1;
+                aw_to_send_d = aw_to_send_q - 1;
+            end
         end
     end
 
     // assign outputs
     assign aw_ready = aw_valid_o & aw_ready_i;
 
     // fall through register to decouple the aw valid signal from the aw ready
-    // now payload is required; just the decoupling of the handshaking signals
+    // no payload is required; just the decoupling of the handshaking signals
     fall_through_register #(
         .T ( logic [0:0] )
     ) i_fall_through_register_decouple_aw_valid (
@@ -180,6 +196,8 @@ module idma_channel_coupler #(
 
     // state
     `FF(aw_to_send_q, aw_to_send_d, '0, clk_i, rst_ni)
+    `FF(aw_to_stall_q, aw_to_stall_d, '0, clk_i, rst_ni)
+    `FF(aw_stall_q, aw_stall_d, '0, clk_i, rst_ni)
 
 
 endmodule

src/backend/idma_init_write.sv

@@ -62,6 +62,10 @@ module idma_init_write #(
     /// INIT write manager port response
     input  write_rsp_t write_rsp_i,
 
+    output logic w_chan_valid_o,
+    output logic w_chan_ready_o,
+    output logic w_chan_first_o,
+
     /// Data from buffer
     input  byte_t [StrbWidth-1:0] buffer_out_i,
     /// Valid from buffer
@@ -151,6 +155,11 @@ module idma_init_write #(
     assign w_dp_ready_o       = write_happening;
     assign write_meta_ready_o = write_happening;
 
+    // Channel management signals
+    assign w_chan_valid_o = write_req_o.req_valid;
+    assign w_chan_ready_o = write_rsp_i.req_ready;
+    assign w_chan_first_o = 1'b1; // always first, no AW channel
+
     //--------------------------------------
     // Write response
     //--------------------------------------

src/backend/idma_obi_write.sv

@@ -61,6 +61,10 @@ module idma_obi_write #(
     /// OBI write manager port response
     input  write_rsp_t write_rsp_i,
 
+    output logic w_chan_valid_o,
+    output logic w_chan_ready_o,
+    output logic w_chan_first_o,
+
     /// Data from buffer
     input  byte_t [StrbWidth-1:0] buffer_out_i,
     /// Valid from buffer
@@ -153,6 +157,11 @@ module idma_obi_write #(
     assign w_dp_ready_o = write_happening;
     assign aw_ready_o   = write_happening;
 
+    // Channel management signals
+    assign w_chan_valid_o = write_req_o.req;
+    assign w_chan_ready_o = write_rsp_i.gnt;
+    assign w_chan_first_o = 1'b1; // always first, no bursting
+
     //--------------------------------------
     // Write response
     //--------------------------------------

src/backend/idma_tilelink_write.sv

@@ -70,6 +70,10 @@ module idma_tilelink_write #(
     /// TileLink write manager port response
     input  write_rsp_t write_rsp_i,
 
+    output logic w_chan_valid_o,
+    output logic w_chan_ready_o,
+    output logic w_chan_first_o,
+
     /// Data from buffer
     input  byte_t [StrbWidth-1:0] buffer_out_i,
     /// Valid from buffer
@@ -254,6 +258,10 @@ module idma_tilelink_write #(
         end
     end
 
+    // Channel management signals
+    assign w_chan_valid_o = write_req_o.a_valid;
+    assign w_chan_ready_o = write_rsp_i.a_ready;
+    assign w_chan_first_o = first_w;
 
     //--------------------------------------
     // Write response

src/backend/tpl/idma_backend.sv.tpl

@@ -371,9 +371,13 @@ _rsp_t ${protocol}_write_rsp_i,
     logic      rsp_valid;
     logic      rsp_ready;
 
-    // Respone Channel valid and ready -> needed for bursting
-    logic r_chan_valid;
-    logic r_chan_ready;
+    // // Respone Channel valid and ready -> needed for bursting
+    // logic r_chan_valid;
+    // logic r_chan_ready;
+
+    logic w_chan_valid;
+    logic w_chan_ready;
+    logic w_chan_first;
 
     //--------------------------------------
     // Reject Zero Length Transfers
@@ -770,8 +774,11 @@ _rsp_t ${protocol}_write_rsp_i,
         .r_dp_busy_o     ( busy_o.r_dp_busy     ),
         .w_dp_busy_o     ( busy_o.w_dp_busy     ),
         .buffer_busy_o   ( busy_o.buffer_busy   ),
-        .r_chan_ready_o  ( r_chan_ready         ),
-        .r_chan_valid_o  ( r_chan_valid         )
+        .w_chan_valid_o  ( w_chan_valid         ),
+        .w_chan_ready_o  ( w_chan_ready         ),
+        .w_chan_first_o  ( w_chan_first         )
+        // .r_chan_ready_o  ( r_chan_ready         ),
+        // .r_chan_valid_o  ( r_chan_valid         )
     );
 
     //--------------------------------------
@@ -803,10 +810,13 @@ _rsp_t ${protocol}_write_rsp_i,
             .clk_i            ( clk_i                       ),
             .rst_ni           ( rst_ni                      ),
             .testmode_i       ( testmode_i                  ),
-            .r_rsp_valid_i    ( r_chan_valid                ),
-            .r_rsp_ready_i    ( r_chan_ready                ),
-            .r_rsp_first_i    ( r_dp_rsp.first              ),
-            .r_decouple_aw_i  ( r_dp_req_out.decouple_aw    ),
+            .w_req_valid_i    ( w_chan_valid                ),
+            .w_req_ready_i    ( w_chan_ready                ),
+            .w_req_first_i    ( w_chan_first                ),
+            // .r_rsp_valid_i    ( r_chan_valid                ),
+            // .r_rsp_ready_i    ( r_chan_ready                ),
+            // .r_rsp_first_i    ( r_dp_rsp.first              ),
+            // .r_decouple_aw_i  ( r_dp_req_out.decouple_aw    ),
             .aw_decouple_aw_i ( \
 % if one_write_port:
 w_req.decouple_aw\