Skip to content

Fix axi includes #82

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
DanielKellerM wants to merge 2 commits into from
Closed

Fix axi includes #82

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
28a36e5
Release v0.6.5
Jul 15, 2025
fdf0fae
guard axi includes; separate response from axi package
DanielKellerM Aug 28, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
26 changes: 14 additions & 12 deletions src/backend/tpl/idma_backend.sv.tpl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,9 @@
// - Thomas Benz <tbenz@iis.ee.ethz.ch>
// - Tobias Senti <tsenti@ethz.ch>

% if ('axi' in used_read_protocols) or ('axi' in used_write_protocols):
`include "axi/typedef.svh"
% endif
`include "idma/guard.svh"

/// The iDMA backend implements an arbitrary 1D copy engine
Expand All @@ -15,9 +17,9 @@ module idma_backend_${name_uniqueifier} #(
parameter int unsigned DataWidth = 32'd16,
/// Address width
parameter int unsigned AddrWidth = 32'd24,
/// AXI user width
/// User width
parameter int unsigned UserWidth = 32'd1,
/// AXI ID width
/// Transaction ID width
parameter int unsigned AxiIdWidth = 32'd1,
/// Number of transaction that can be in-flight concurrently
parameter int unsigned NumAxInFlight = 32'd2,
Expand All @@ -44,7 +46,7 @@ module idma_backend_${name_uniqueifier} #(
parameter bit MaskInvalidData = 1'b1,
/// Should hardware legalization be present? (recommended)
/// If not, software legalization is required to ensure the transfers are
/// AXI4-conformal
/// Bus-spec conformal
parameter bit HardwareLegalizer = 1'b1,
/// Reject zero-length transfers
parameter bit RejectZeroTransfers = 1'b1,
Expand Down Expand Up @@ -207,11 +209,11 @@ _rsp_t ${protocol}_write_rsp_i,
} r_dp_req_t;

/// The datapath read response type provides feedback from the read part of the datapath:
/// - `resp`: The response from the R channel of the AXI4 manager interface
/// - `last`: The last flag from the R channel of the AXI4 manager interface
/// - `resp`: Protocol-agnostic response code (matches AXI encoding width when AXI is used)
/// - `last`: The last flag of the read response channel
/// - `first`: Is the current item first beat in the burst
typedef struct packed {
axi_pkg::resp_t resp;
logic [1:0] resp;
logic last;
logic first;
} r_dp_rsp_t;
Expand All @@ -229,15 +231,15 @@ _rsp_t ${protocol}_write_rsp_i,
offset_t offset;
offset_t tailer;
offset_t shift;
axi_pkg::len_t num_beats;
tf_len_t num_beats;
logic is_single;
} w_dp_req_t;

/// The datapath write response type provides feedback from the write part of the datapath:
/// - `resp`: The response from the B channel of the AXI4 manager interface
/// - `user`: The user field from the B channel of the AXI4 manager interface
/// - `resp`: Protocol-agnostic response code
/// - `user`: User field propagated to the write response (when supported)
typedef struct packed {
axi_pkg::resp_t resp;
logic [1:0] resp;
user_t user;
} w_dp_rsp_t;

Expand Down Expand Up @@ -462,7 +464,7 @@ _rsp_t ${protocol}_write_rsp_i,
);

// local signal holding the length -> explicitly only doing the computation once
axi_pkg::len_t len;
tf_len_t len;
assign len = ((idma_req_i.length + idma_req_i.src_addr[OffsetWidth-1:0] -
'd1) >> OffsetWidth);

Expand Down Expand Up @@ -917,7 +919,7 @@ w_req.decouple_aw || (w_req.w_dp_req.dst_protocol inside {\
$fatal(1, "Parameter AxiIdWidth has to be > 0!");
axi_data_width : assert(DataWidth inside {32'd16, 32'd32, 32'd64, 32'd128, 32'd256,
32'd512, 32'd1024}) else
$fatal(1, "Parameter DataWidth has to be at least 16 and inside the AXI4 spec!");
$fatal(1, "Parameter DataWidth has to be at least 16 and a supported bus width!");
axi_user_width : assert(UserWidth > 32'd0) else
$fatal(1, "Parameter UserWidth has to be > 0!");
num_ax_in_flight : assert(NumAxInFlight > 32'd1) else
Expand Down
40 changes: 34 additions & 6 deletions src/backend/tpl/idma_backend_synth.sv.tpl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,21 +6,29 @@
// - Thomas Benz <tbenz@iis.ee.ethz.ch>
// - Tobias Senti <tsenti@ethz.ch>

% if ('axi' in used_read_protocols) or ('axi' in used_write_protocols):
`include "axi/typedef.svh"
% endif
% if ('axi_stream' in used_read_protocols) or ('axi_stream' in used_write_protocols):
`include "axi_stream/typedef.svh"
`include "idma/typedef.svh"
% endif
% if ('obi' in used_read_protocols) or ('obi' in used_write_protocols):
`include "obi/typedef.svh"
% endif
% if ('tilelink' in used_read_protocols) or ('tilelink' in used_write_protocols):
`include "tilelink/typedef.svh"
% endif
`include "idma/typedef.svh"

/// Synthesis wrapper for the iDMA backend. Unpacks all the interfaces to simple logic vectors
module idma_backend_synth_${name_uniqueifier} #(
/// Data width
parameter int unsigned DataWidth = 32'd32,
/// Address width
parameter int unsigned AddrWidth = 32'd32,
/// AXI user width
/// User width
parameter int unsigned UserWidth = 32'd1,
/// AXI ID width
/// Transaction ID width
parameter int unsigned AxiIdWidth = 32'd1,
/// Number of transaction that can be in-flight concurrently
parameter int unsigned NumAxInFlight = 32'd3,
Expand Down Expand Up @@ -52,7 +60,7 @@ module idma_backend_synth_${name_uniqueifier} #(
%endif
/// Should hardware legalization be present? (recommended)
/// If not, software legalization is required to ensure the transfers are
/// AXI4-conformal
/// bus-spec conformal
parameter bit HardwareLegalizer = 1'b1,
/// Reject zero-length transfers
parameter bit RejectZeroTransfers = 1'b1,
Expand Down Expand Up @@ -95,6 +103,7 @@ module idma_backend_synth_${name_uniqueifier} #(
input addr_t req_dst_addr_i,
input idma_pkg::protocol_e req_src_protocol_i,
input idma_pkg::protocol_e req_dst_protocol_i,
% if ('axi' in used_read_protocols) or ('axi' in used_write_protocols):
input id_t req_axi_id_i,
input axi_pkg::burst_t req_src_burst_i,
input axi_pkg::cache_t req_src_cache_i,
Expand All @@ -108,6 +117,7 @@ module idma_backend_synth_${name_uniqueifier} #(
input axi_pkg::prot_t req_dst_prot_i,
input axi_pkg::qos_t req_dst_qos_i,
input axi_pkg::region_t req_dst_region_i,
% endif
input logic req_decouple_aw_i,
input logic req_decouple_rw_i,
input logic [2:0] req_src_max_llen_i,
Expand All @@ -119,7 +129,9 @@ module idma_backend_synth_${name_uniqueifier} #(
output logic rsp_valid_o,
input logic rsp_ready_i,

% if ('axi' in used_read_protocols) or ('axi' in used_write_protocols):
output axi_pkg::resp_t rsp_cause_o,
% endif
output idma_pkg::err_type_t rsp_err_type_o,
output addr_t rsp_burst_addr_o,
output logic rsp_error_o,
Expand Down Expand Up @@ -166,7 +178,7 @@ ${database[protocol]['typedefs']}
% endif
% endfor

/// Option struct: AXI4 id as well as AXI and backend options
/// Option struct: transaction id and protocol/backend options
/// - `last`: a flag can be set if this transfer is the last of a set of transfers
`IDMA_TYPEDEF_OPTIONS_T(options_t, id_t)

Expand All @@ -177,10 +189,18 @@ ${database[protocol]['typedefs']}
`IDMA_TYPEDEF_REQ_T(idma_req_t, tf_len_t, addr_t, options_t)

/// 1D iDMA response payload:
/// - `cause`: the AXI response
/// - `cause`: protocol response code
/// - `err_type`: type of the error: read, write, internal, ...
/// - `burst_addr`: the burst address where the issue error occurred
% if ('axi' in used_read_protocols) or ('axi' in used_write_protocols):
`IDMA_TYPEDEF_ERR_PAYLOAD_T(err_payload_t, addr_t)
% else:
typedef struct packed {
logic [1:0] cause;
idma_pkg::err_type_t err_type;
addr_t burst_addr;
} err_payload_t;
% endif

/// 1D iDMA response type:
/// - `last`: the response of the request that was marked with the `opt.last` flag
Expand Down Expand Up @@ -364,6 +384,7 @@ ${p}_${database[p]['write_meta_channel']}_width\
assign idma_req.length = req_length_i;
assign idma_req.opt.src_protocol = req_src_protocol_i;
assign idma_req.opt.dst_protocol = req_dst_protocol_i;
% if ('axi' in used_read_protocols) or ('axi' in used_write_protocols):
assign idma_req.opt.axi_id = req_axi_id_i;
assign idma_req.opt.dst.cache = req_dst_cache_i;
assign idma_req.opt.dst.burst = req_dst_burst_i;
Expand All @@ -377,6 +398,11 @@ ${p}_${database[p]['write_meta_channel']}_width\
assign idma_req.opt.src.lock = req_src_lock_i;
assign idma_req.opt.src.prot = req_src_prot_i;
assign idma_req.opt.src.region = req_src_region_i;
% else:
assign idma_req.opt.axi_id = '0;
assign idma_req.opt.dst = '0;
assign idma_req.opt.src = '0;
% endif
assign idma_req.opt.beo.dst_reduce_len = req_dst_reduce_len_i;
assign idma_req.opt.beo.src_reduce_len = req_src_reduce_len_i;
assign idma_req.opt.beo.dst_max_llen = req_dst_max_llen_i;
Expand All @@ -385,7 +411,9 @@ ${p}_${database[p]['write_meta_channel']}_width\
assign idma_req.opt.beo.decouple_aw = req_decouple_aw_i;
assign idma_req.opt.last = req_last_i;

% if ('axi' in used_read_protocols) or ('axi' in used_write_protocols):
assign rsp_cause_o = idma_rsp.pld.cause;
% endif
assign rsp_err_type_o = idma_rsp.pld.err_type;
assign rsp_burst_addr_o = idma_rsp.pld.burst_addr;
assign rsp_error_o = idma_rsp.error;
Expand Down
4 changes: 3 additions & 1 deletion src/backend/tpl/idma_legalizer.sv.tpl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -665,10 +665,12 @@ ${database[protocol]['legalizer_write_data_path']}
//--------------------------------------
// Assertions
//--------------------------------------
// only support the decomposition of incremental bursts
// only support the decomposition of incremental bursts (AXI only)
% if ('axi' in used_read_protocols) or ('axi' in used_write_protocols):
`ASSERT_NEVER(OnlyIncrementalBurstsSRC, (ready_o & valid_i &
req_i.opt.src.burst != axi_pkg::BURST_INCR), clk_i, !rst_ni)
`ASSERT_NEVER(OnlyIncrementalBurstsDST, (ready_o & valid_i &
req_i.opt.dst.burst != axi_pkg::BURST_INCR), clk_i, !rst_ni)
% endif

endmodule
9 changes: 5 additions & 4 deletions target/rtl/.gitignore
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
Bender.yml
include
*.sv
*.hjson
# Deactivated by deploy.py
# Bender.yml
# include
# *.sv
# *.hjson
Loading
Loading