fix: Error handler valid/ready protocol violations

[DanielKellerM]

Summary

• Guard FSM state transitions on rsp_ready_i so rsp_valid_o is not deasserted before the handshake completes
• Add missing eh_valid_i check in WAIT_LAST_W to prevent sampling garbage eh_i data (copy-paste omission from WAIT state)

Detailed

Bug 1: When a write error occurs and the downstream consumer back-pressures (rsp_ready_i=0), the old FSM unconditionally transitions out of IDLE. On the next cycle, the defaults kick in and rsp_valid_o drops to 0 even though the handshake never completed. That's a valid/ready protocol violation once you assert valid, you can't retract it before ready.

Bug 2: In WAIT_LAST_W, the old code checked eh_i == CONTINUE without first gating on eh_valid_i. So whatever garbage happened to be on the eh_i bus could trigger eh_ready_o=1 and a state transition, even with no valid request from the error handler frontend.

Test plan

• Questa simulation: simple.txt and error_simple.txt pass (0 errors)
• CI regression

[Copilot]

Pull request overview

Fixes the iDMA backend error-handler FSM to comply with valid/ready handshake semantics by preventing premature rsp_valid_o deassertion and avoiding sampling eh_i when eh_valid_i is low.

Changes:

• Gate error-state transitions in IDLE on rsp_ready_i so the FSM only leaves IDLE after the response handshake completes.
• Add missing eh_valid_i guard in WAIT_LAST_W, matching the existing WAIT behavior.

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