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5e5019a
cfg: Rename to `enable_narrow_collectives` in `snitch_cluster.json`
colluca Sep 26, 2025
5830d2d
cluster_tile.sv: Update name of `user_t` to `user_narrow_t`
colluca Sep 26, 2025
a4bfb06
cluster_tile.sv: Add and tie off DCA interface
colluca Sep 26, 2025
917dfba
iis-env.sh: Bump LLVM toolchain
colluca Sep 26, 2025
e5decf5
requirements.txt: Bump peakrdl-rawheader
colluca Sep 26, 2025
297ee58
UNDO: Add separate SNRT_ENABLE_NARROW_REDUCTION
colluca Sep 26, 2025
4955f98
bender: Bump `snitch_cluster` and `axi`
colluca Sep 26, 2025
cc4231e
sw: Initialize destination arrays in `dma_multicast.c`
colluca Sep 26, 2025
3a9d835
bender: Bump iDMA to include DMUSER instruction
colluca Sep 27, 2025
479cf69
cfg: Set `enable_wide_collectives` in snitch_cluster.json
colluca Sep 27, 2025
15b9b28
hw: Pass cluster base offset to cluster tile
colluca Sep 27, 2025
38344f4
sw: Integrate Lorenzo's microbenchmark
Lore0599 Aug 7, 2025
cc6f2d0
python-venv: Install Snitch in editable mode
colluca Sep 29, 2025
0c9017b
dma_multicast.c: Fix missing `LENGTH` variable
colluca Sep 29, 2025
4df0236
sw: Build Picobello's Snitch tests using Snitch's rules
colluca Sep 29, 2025
62090d7
dma_multicast.c: Use `snrt_align_up` function
colluca Sep 29, 2025
c3b9c51
make: Enable running simulations in different directories
colluca Sep 29, 2025
651b303
hw: Integrate updated parallel reduction support
Lore0599 Sep 30, 2025
0ee875e
hw: Integrate virtual channel + offload reduction
Lore0599 Oct 2, 2025
28fd2fa
hw: Report destination address of collectives attempted in memtile
colluca Oct 4, 2025
59d62dc
experiments/mcast: Set up Python-based experiment infrastructure
colluca Sep 29, 2025
0078649
hw: Add two physical channels on wide_out interface to local port
colluca Oct 5, 2025
0d77e66
gitignore: Ignore `__pycache__` folders
colluca Oct 8, 2025
b68733d
sw: Split runtime into impl and src folder
colluca Oct 8, 2025
bd0eabc
sw: Add `pb_team` and `pb_sync` functions
colluca Oct 8, 2025
c7cf4c2
experiments: Add wide multicast experiments
colluca Oct 8, 2025
fb21f91
hw: Fix user width to carry full atomic ID
colluca Oct 9, 2025
d254e3f
experiments: Add barrier experiments
colluca Oct 9, 2025
49cc653
sw: Extend mesh communicator to have an arbitrary base cluster
colluca Oct 15, 2025
4091ecf
sw: Add more complex barrier tests
colluca Oct 15, 2025
ec95516
experiments: Extend `picobello.py` to support kernel experiments
colluca Oct 15, 2025
dddc5f5
sw: Add `summa_gemm` kernel
colluca Oct 15, 2025
4c5b67a
experiments: Add SUMMA GEMM experiments
colluca Oct 15, 2025
5a1c6fd
hw: Fix reduction + VC Read/Write
Oct 5, 2025
397cb0c
hw: Align with latest FlooNoC collective configuration
Lore0599 Oct 9, 2025
89787a8
hw: Add paramterization for internal offload cut
Lore0599 Oct 17, 2025
7a79213
hw: Adapt Picobello to multi ejection channels
Lore0599 Oct 17, 2025
20db417
sw: Add Snitch BLAS headers to tests' include directory
colluca Oct 21, 2025
5eb6959
experiments: Add callback for hardware build
colluca Oct 22, 2025
3d04ce9
sw: Enable communicator creation from arbitrary communicators
colluca Oct 22, 2025
a4d446d
experiments: Update barrier experiments
colluca Oct 23, 2025
c8a21a4
hw(cluster): Increase atomic txns to 3
fischeti Oct 23, 2025
04d6566
hw: Use manual floogen package
fischeti Oct 23, 2025
adc19dd
experiments: Add wide reduction experiments
colluca Oct 21, 2025
e3a7279
bender: Bump common_cells
Lore0599 Oct 28, 2025
8f777aa
Update plots for paper
colluca Oct 29, 2025
f40cebe
Update plots for paper again
colluca Oct 30, 2025
6213bc2
More fixes for the paper
colluca Oct 30, 2025
a976c11
modify 2d reduction plot, also add the hyperbank reduction(tree not s…
imchenwu Oct 30, 2025
9d48f2b
Final amendments for submitted paper
colluca Nov 11, 2025
550c9ae
Fix bug in tree multicast model
colluca Nov 11, 2025
1c24239
Clean reduction benchmark
colluca Dec 12, 2025
2215613
Bump dependencies
colluca Dec 17, 2025
9b3718c
Update software to new Snitch collective API
colluca Dec 17, 2025
2ed76da
Bump Snitch LLVM toolchain
colluca Dec 17, 2025
e5c73be
Remove legacy `dma_multicast` experiments
colluca Dec 17, 2025
8b1c787
Cleanup reduction experiments removing hw generic
colluca Dec 17, 2025
e3a6f54
Fix lint error in picobello.py
colluca Dec 17, 2025
a30d3a9
Cleanup summa_gemm data configuration
colluca Dec 17, 2025
8f0a264
Remove prints from `dma_multicast_v2.c`
colluca Dec 17, 2025
6936a3b
Add description in tests
colluca Dec 17, 2025
5d2e308
Rename dma_multicast_v2 experiments and benchmark
colluca Dec 17, 2025
cd2764c
hw: Adapt SoC to multiple physical channels
Lore0599 Nov 22, 2025
b5bc432
hw: Align with credit based VC
Lore0599 Nov 24, 2025
f38c190
hw: Add UnstableValid VC implementation
colluca Nov 25, 2025
dcc68f8
vsim.mk: Use `BENDER` variable
colluca Nov 24, 2025
48605df
hw: Align picobello with FlooNoC VC
Lore0599 Dec 17, 2025
625d714
Fix setuptools
Lore0599 Feb 26, 2026
064d976
Add experiments in CI
Lore0599 Feb 26, 2026
40dcf3c
ci: Reduce experiments size for CI usage
Lore0599 Feb 27, 2026
508db96
Improve make flow
Lore0599 Feb 27, 2026
73cb500
Bump FlooNoC
Lore0599 Mar 2, 2026
5403ba4
Align new floogen CLI
Lore0599 Mar 2, 2026
657ea52
Remove unused cfg par
Lore0599 Mar 4, 2026
616b001
Bump floonoc without coll loopback option
Lore0599 Mar 4, 2026
574ee65
hw: Align with new offload interface
Lore0599 Mar 5, 2026
2b4f86b
hw: Enable multi phys for performance boost
Lore0599 Mar 6, 2026
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3 changes: 2 additions & 1 deletion .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -8,9 +8,10 @@
.bender
working_dir/

# Python virtual environment
# Python virtual environment and caches
.cache/pip
.venv
__pycache__

# Generated source files
.generated
Expand Down
26 changes: 26 additions & 0 deletions .gitlab-ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -57,6 +57,9 @@ chs-sw:

vsim-compile:
stage: build
extends:
- .cache-deps
- .init-env
needs:
- generate-rtl
variables:
Expand Down Expand Up @@ -101,6 +104,29 @@ sim-vsim:
paths:
- transcript

#####################
# Run Experiments #
#####################

sim-exps:
stage: run
extends:
- .cache-deps
- .init-env
needs:
- chs-sw
- sn-sw
- vsim-compile
parallel:
matrix:
- EXPERIMENT: multicast
- EXPERIMENT: reduction
- EXPERIMENT: barrier
script:
- cd experiments/$EXPERIMENT && ./experiments.py --ci --actions sw run -j
artifacts:
expire_in: 7 days

###################
# Physical Design #
###################
Expand Down
1 change: 0 additions & 1 deletion .gitlab/common.yml
Original file line number Diff line number Diff line change
Expand Up @@ -68,7 +68,6 @@ variables:
script:
- make sn-tests DEBUG=ON
- make sn-apps DEBUG=ON
- make pb-sn-tests
artifacts:
paths:
- sw/snitch/tests/build/*.elf
Expand Down
2 changes: 1 addition & 1 deletion .gitlab/sw-tests.yml
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: $SN_BUILD_DIR/non_null_exitcode.elf, NZ_EXIT_CODE: 896 }
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: $SN_BUILD_DIR/multicluster_atomics.elf }
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: $SN_BUILD_DIR/mcast_barrier.elf }
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: $SN_BUILD_DIR/dma_multicast.elf }
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: $SN_BUILD_DIR/multicast_benchmark.elf }
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: $SN_BUILD_DIR/multi_mcast.elf }
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: $SN_BUILD_DIR/row_col_mcast.elf }
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: $SN_BUILD_DIR/access_spm.elf }
Expand Down
24 changes: 16 additions & 8 deletions Bender.lock
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ packages:
- obi_peripherals
- register_interface
axi:
revision: bec548fa2a9b18cbd7531105bb1fdf481ea8ad49
revision: 06410c36819924e32db2afa428d244dbdbcd5d4e
version: null
source:
Git: https://github.com/colluca/axi.git
Expand Down Expand Up @@ -129,8 +129,8 @@ packages:
- common_cells
- register_interface
cluster_icache:
revision: 64e21ae455bbdde850c4df13bef86ea55ac42537
version: 0.2.0
revision: 1642961b9561513f283674efc2c90f24855e8d39
version: 0.3.1
source:
Git: https://github.com/pulp-platform/cluster_icache.git
dependencies:
Expand All @@ -146,7 +146,7 @@ packages:
dependencies:
- common_cells
common_cells:
revision: e1c09c75775c5f03eb45906d5145dbd2f5bcfb95
revision: ca9d577f2fbc45ec557ab4e0905bbfc154441540
version: null
source:
Git: https://github.com/pulp-platform/common_cells.git
Expand Down Expand Up @@ -207,7 +207,7 @@ packages:
Path: .deps/fhg_spu_cluster
dependencies: []
floo_noc:
revision: ea35a9909d60d552bbdafc7e898590f326b1898a
revision: 8d19d926fbc9174984a67d76f349d82ea117c443
version: null
source:
Git: https://github.com/pulp-platform/FlooNoC.git
Expand All @@ -216,7 +216,15 @@ packages:
- axi_riscv_atomics
- common_cells
- common_verification
- floo_noc_pd
- fpnew
- idma
floo_noc_pd:
revision: null
version: null
source:
Path: working_dir/floo_noc/./pd
dependencies: []
fpnew:
revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315
version: null
Expand Down Expand Up @@ -266,8 +274,8 @@ packages:
dependencies:
- tech_cells_generic
idma:
revision: 7829f71691a62c1e2e5e3230f370f222c7a83087
version: null
revision: 28a36e5e07705549e59fc33db96ab681bc1ca88e
version: 0.6.5
source:
Git: https://github.com/pulp-platform/iDMA.git
dependencies:
Expand Down Expand Up @@ -383,7 +391,7 @@ packages:
- common_cells
- register_interface
snitch_cluster:
revision: 5d6c957c70e3824e2330d8308eb904724cd41cbe
revision: ecf876f5d8726c6424970c99c5e91f83aaedeacd
version: null
source:
Git: https://github.com/pulp-platform/snitch_cluster.git
Expand Down
8 changes: 4 additions & 4 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -9,11 +9,11 @@ package:

dependencies:
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: "0.4.5" }
axi: { git: "https://github.com/pulp-platform/axi.git", version: "0.39.6" }
axi: { git: "https://github.com/colluca/axi.git", rev: "multicast" }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: "snitch" }
cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: "picobello" }
snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: "5d6c957c70e3824e2330d8308eb904724cd41cbe" }
floo_noc: { git: "https://github.com/pulp-platform/FlooNoC.git", rev: "develop" }
snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: "main" }
floo_noc: { git: "https://github.com/pulp-platform/FlooNoC.git", rev: "reduction-vc-rebase" }
obi: { git: "https://github.com/pulp-platform/obi.git", rev: "acfcd0f80c7539aa8da7821a66d9acf2074a5b4e" }
redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: "picobello" }
hci: { git: "https://github.com/pulp-platform/hci.git", rev: "06fcba671e060f2e1b03b7ebe2d3e719f1557099" }
Expand All @@ -36,7 +36,7 @@ sources:
- target: pb_gen_rtl
files:
# Level 0.0
- .generated/floo_picobello_noc_pkg.sv
- floo_picobello_noc_pkg_REDUCTION.sv
- .generated/snitch_cluster_pkg.sv
- .generated/pb_soc_regs_pkg.sv
# Level 0.1
Expand Down
43 changes: 24 additions & 19 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -20,20 +20,23 @@ SN_ROOT = $(shell $(BENDER) path snitch_cluster)
FLOO_ROOT = $(shell $(BENDER) path floo_noc)

# Executables
BENDER ?= bender -d $(PB_ROOT)
BENDER ?= bender --suppress W22 -d $(PB_ROOT)
FLOO_GEN ?= floogen
VERIBLE_FMT ?= verible-verilog-format
VERIBLE_FMT_ARGS ?= --flagfile .verilog_format --inplace --verbose
PEAKRDL ?= peakrdl

# Tiles configuration
SN_CLUSTERS = $(shell $(FLOO_GEN) -c $(FLOO_CFG) --query endpoints.cluster.num 2>/dev/null)
L2_TILES = $(shell $(FLOO_GEN) -c $(FLOO_CFG) --query endpoints.l2_spm.num 2>/dev/null)
SN_CLUSTERS = $(shell $(FLOO_GEN) query -c $(FLOO_CFG) endpoints.cluster.num 2>/dev/null)
L2_TILES = $(shell $(FLOO_GEN) query -c $(FLOO_CFG) endpoints.l2_spm.num 2>/dev/null)

# Bender prerequisites
BENDER_YML = $(PB_ROOT)/Bender.yml
BENDER_LOCK = $(PB_ROOT)/Bender.lock

$(PB_GEN_DIR):
mkdir -p $@

################
# Bender flags #
################
Expand All @@ -45,7 +48,7 @@ SIM_TARGS += -t simulation -t test -t idma_test
# systemRDL #
#############

PB_RDL_ALL += $(PB_GEN_DIR)/picobello.rdl
PB_RDL_ALL += $(PB_GEN_DIR)/picobello_addrmap.rdl
PB_RDL_ALL += $(PB_GEN_DIR)/fll.rdl $(PB_GEN_DIR)/pb_chip_regs.rdl
PB_RDL_ALL += $(PB_GEN_DIR)/snitch_cluster.rdl
PB_RDL_ALL += $(wildcard $(PB_ROOT)/cfg/rdl/*.rdl)
Expand All @@ -58,14 +61,14 @@ $(PB_GEN_DIR)/pb_soc_regs.sv: $(PB_GEN_DIR)/pb_soc_regs_pkg.sv
$(PB_GEN_DIR)/pb_soc_regs_pkg.sv: $(PB_ROOT)/cfg/rdl/pb_soc_regs.rdl
$(PEAKRDL) regblock $< -o $(PB_GEN_DIR) --cpuif apb4-flat --default-reset arst_n -P Num_Clusters=$(SN_CLUSTERS) -P Num_Mem_Tiles=$(L2_TILES)

$(PB_GEN_DIR)/picobello.rdl: $(FLOO_CFG)
$(FLOO_GEN) -c $(FLOO_CFG) -o $(PB_GEN_DIR) --rdl --rdl-as-mem --rdl-memwidth=32
$(PB_GEN_DIR)/picobello_addrmap.rdl: $(FLOO_CFG)
$(FLOO_GEN) rdl -c $(FLOO_CFG) -o $(PB_GEN_DIR) --as-mem --memwidth=32

# Those are dummy RDL files, for generation without access to the PD repository.
$(PB_GEN_DIR)/fll.rdl $(PB_GEN_DIR)/pb_chip_regs.rdl:
$(PB_GEN_DIR)/fll.rdl $(PB_GEN_DIR)/pb_chip_regs.rdl: | $(PB_GEN_DIR)
@touch $@

$(PB_GEN_DIR)/pb_addrmap.h: $(PB_GEN_DIR)/picobello.rdl $(PB_RDL_ALL)
$(PB_GEN_DIR)/pb_addrmap.h: $(PB_GEN_DIR)/picobello_addrmap.rdl $(PB_RDL_ALL)
$(PEAKRDL) c-header $< $(PEAKRDL_INCLUDES) $(PEAKRDL_DEFINES) -o $@ -i -b ltoh

$(PB_GEN_DIR)/pb_addrmap.svh: $(PB_RDL_ALL)
Expand Down Expand Up @@ -130,12 +133,12 @@ endif

floo-hw-all: $(PB_GEN_DIR)/floo_picobello_noc_pkg.sv
$(PB_GEN_DIR)/floo_picobello_noc_pkg.sv: $(FLOO_CFG) | $(PB_GEN_DIR)
$(FLOO_GEN) -c $(FLOO_CFG) -o $(PB_GEN_DIR) --only-pkg $(FLOO_GEN_FLAGS)
$(FLOO_GEN) pkg -c $(FLOO_CFG) -o $(PB_GEN_DIR) $(FLOO_GEN_FLAGS)


floo-clean:
rm -f $(PB_GEN_DIR)/floo_picobello_noc_pkg.sv
rm -f $(PB_GEN_DIR)/picobello.rdl
rm -f $(PB_GEN_DIR)/picobello_addrmap.rdl

###################
# Physical Design #
Expand Down Expand Up @@ -172,16 +175,16 @@ clean-pd:

PB_HW_ALL += $(CHS_HW_ALL)
PB_HW_ALL += $(CHS_SIM_ALL)
PB_HW_ALL += $(PB_GEN_DIR)/floo_picobello_noc_pkg.sv
PB_HW_ALL += $(PB_RDL_HW_ALL)
PB_HW_ALL += update-sn-cfg

.PHONY: picobello-hw-all picobello-clean clean
.PHONY: picobello-hw-all picobello-hw-clean clean

picobello-hw-all all: $(PB_HW_ALL) update-sn-cfg sn-hw-all floo-hw-all

picobello-hw-all all: $(PB_HW_ALL) sn-hw-all
$(MAKE) $(PB_HW_ALL)
picobello-hw-clean: sn-hw-clean floo-clean
rm -rf $(PB_HW_ALL)

picobello-hw-clean clean: sn-hw-clean floo-clean
clean: picobello-hw-clean
rm -rf $(BENDER_ROOT)

############
Expand All @@ -195,6 +198,7 @@ include $(PB_ROOT)/sw/sw.mk
##############

TB_DUT = tb_picobello_top
SIM_DIR = $(PB_ROOT)

include $(PB_ROOT)/target/sim/vsim/vsim.mk
include $(PB_ROOT)/target/sim/traces.mk
Expand All @@ -221,13 +225,14 @@ python-venv: .venv
.venv:
$(BASE_PYTHON) -m venv $@
. $@/bin/activate && \
python -m pip install --upgrade pip setuptools && \
python -m pip install --cache-dir $(PIP_CACHE_DIR) -r requirements.txt && \
python -m pip install --upgrade pip "setuptools<81" && \
python -m pip install --no-build-isolation --cache-dir $(PIP_CACHE_DIR) -r requirements.txt && \
python -m pip install --cache-dir $(PIP_CACHE_DIR) $(shell $(BENDER) path floo_noc) --no-deps && \
python -m pip install --cache-dir $(PIP_CACHE_DIR) "$(shell $(BENDER) path snitch_cluster)[kernels]"
python -m pip install --cache-dir $(PIP_CACHE_DIR) -e "$(shell $(BENDER) path snitch_cluster)[kernels]"

python-venv-clean:
rm -rf .venv
rm -rf $(PIP_CACHE_DIR)

verible-fmt:
$(VERIBLE_FMT) $(VERIBLE_FMT_ARGS) $(shell $(BENDER) script flist $(SIM_TARGS) --no-deps)
Expand Down
8 changes: 5 additions & 3 deletions cfg/snitch_cluster.json
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,6 @@
addr_width: 48,
data_width: 64,
atomic_id_width: 5, // clog2(#clusters + 2)
user_width: 53, // addr_width + atomic_id_width
tcdm: {
size: 128,
banks: 32,
Expand All @@ -26,13 +25,16 @@
dma_req_fifo_depth: 8,
narrow_trans: 4,
wide_trans: 32,
dma_user_width: 48,
enable_multicast: true,
enable_narrow_collectives: true,
enable_wide_collectives: true,
enable_dca: true,
dca_data_width: 512,
cluster_base_expose: true,
alias_region_enable: true,
alias_region_base: 0x30000000,
num_exposed_wide_tcdm_ports: 1,
narrow_axi_port_expose: true,
collective_width: 4,
enable_external_interrupts: true,
vm_support: false,
// Timing parameters
Expand Down
6 changes: 6 additions & 0 deletions experiments/.gitignore
Original file line number Diff line number Diff line change
@@ -0,0 +1,6 @@
build/
runs/
plots/
results/
data/
hw/
9 changes: 9 additions & 0 deletions experiments/barrier/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
# Copyright 2025 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
# Luca Colagrande <colluca@iis.ee.ethz.ch>

from . import plot, experiments, fit

__all__ = ["plot", "experiments", "fit"]
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