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hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.rdl
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hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.rdl
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hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv
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Simple question, why? 😁 |
SystemRDL together with PeakRDL provides great infrastructure for register files, and especially can tie together these address maps hierarchically, allowing for a full view of an SoC. The language is properly specified and more widely accepted than opentitan's hjson format. Furthermore, most industry-standard IPs use APB as a configuration interface, which is also directly supported here in favor of register interface (feel free look into adding register_interface ports to peakrdl-regblock if you prefer this). Ensuring the registers are generated from the rdl description further ensures a single source of truth for the system's mapping. Pulling together rdl files, adding memory blocks, and tying these together allows for direct checking of address map collisions, and ultimately provides a top-level view of a system's address space, something that would require a significant amount of manual work with the current infrastructure. |
I see now that it's an Accelera standard. Cool, thanks @micprog :) |
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Currently, some tests are failing because the |
hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv
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hjsonandreggenwithrdlandpeakrdlrespectively