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Jul 6, 2022
v/src/LaneDiv.scala
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| import chisel3._ | ||
| import chisel3.util._ | ||
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| case class LaneDivParameter(dataWidth: Int, maskWidth: Int) |
v/src/LaneFFO.scala
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| import chisel3._ | ||
| import chisel3.util._ | ||
| import freechips.rocketchip.util.{OH1ToUInt, leftOR} |
v/src/LaneLogic.scala
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| val resp: UInt = IO(Output(UInt(param.ELEN.W))) | ||
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| resp := VecInit(src.map(_.asBools).transpose.map { case Seq(sr0, sr1) => | ||
| val bitCalculate = Module(new LaneBitLogic) |
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v/src/LaneMul.scala
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| import chisel3._ | ||
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| class LaneMul(param: VectorParameters) extends Module { |
v/src/LanePopCount.scala
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| import chisel3._ | ||
| import chisel3.util.PopCount | ||
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| case class LanePopCountParameter(inputWidth: Int, outputWidth: Int) |
v/src/LaneShifter.scala
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| import chisel3._ | ||
| import chisel3.util._ | ||
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| case class LaneShifterParameter(dataWidth: Int, maskWidth: Int, shifterSizeBit: Int) |
added 24 commits
September 6, 2022 12:18
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