Advanced Architecture Labs with CVA6

LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peripherals.

LiteX CVA6 - Fixed integration of the CPU into LiteX SoC generator

Provides baremetal support for the CVA6 COREV APU on GENESYS2

Yocto layer for OpenHWGroup

Garuda: CVXIF coprocessor optimizing batch-1 attention microkernels with 7.5-9× lower p99 latency. RISC-V INT8 MAC accelerator for transformer inference.

These scripts are used in a Vivado project, to implement jtag to axi transactions. The general project is to run baremetal cpp code on Ariane RISC-V core

Our work as students (Team Breizh Hat) for the national CVA6 softcore hackathon organized by Thales Group

Implementation of TAGE and GShare branch predictors for the CVA6 (Ariane) open-source RISC-V core.

Investigation of RVA23 profile compliance in the CVA6 (Ariane) RISC-V core, including RTL analysis, extension support evaluation, and potential implementation paths for missing ISA extensions.

This repository contains performance measurement results for a RISC-V CVA6 core running on a PYNQ-Z2 FPGA.