The MOD-10 counter was functionally verified using a Verilog testbench to validate reset, load, increment, and rollover operations. Out of 2987 executed test cases, 2937 passed successfully, achieving a verification accuracy of approximately 98.33%.
AES-128 (Advanced Encryption Standard 128-bit) module written in Verilog for FPGA/ASIC use.
SHA-256 (Secure Hash Algorithm 256-bit) hardware is implemented in Verilog and C and verifcated in SystemVerilog.
Implementing a 4-tap FIR filter on the Intel DE1-SoC FPGA using Verilog HDL
An open-source Verilog implementation of UART featuring 8-bit and 32-bit architectures with simulation support for efficient data exchange.
RTL code of an 8-bit CPU designed in Verilog.
This repository contains the Verilog design and testbench for a 8x1 Multiplexer. It uses three select lines to choose one of the eight inputs (A0–A7) and drive it to a single output based on the logic expression: Y = S2'S1'S0'A0 + S2'S1'S0A1 + S2'S1S0'A2 + S2'S1S0A3 + S2S1'S0'A4 + S2S1'S0A5 + S2S1S0'A6 + S2S1S0A7
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