feat: Specialized packing strategy for decoupling capacitors

[natinew77-creator]

/claim #15

Implements a specialized packing strategy for decoupling capacitors to ensure neat, linear layouts.

Changes

• Added packDecouplingCaps method to SingleInnerPartitionPackingSolver.
• Detects decoupling capacitor partitions.
• Sorts capacitors based on the pin index of the main connected chip (e.g., U3.1, U3.10...).
• Arranges them in a linear row with configurable spacing.

Verification

Added tests/DecouplingCapacitorPacking.test.ts which verifies:

• Decoupling caps are grouped.
• They are sorted matching the main chip's pin order.
• They are placed linearly.

The test output confirms the linear arrangement:

Group: decap_group_U3__GND__V3_3
  Positions:
  - C12: y=5.96
  - C14: y=5.96
  - C8:  y=5.96
  ... (all Y coordinates identical)

[vercel]

@natinew77-creator is attempting to deploy a commit to the tscircuit Team on Vercel.

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[natinew77-creator]

Ready for review! If there is any feedback, I am happy to address it.

[techmannih]

@natinew77-creator Join our discord for discussion and you can also drop your pr link in reviewme channel on the discord for fast reviews
https://discord.gg/hW5GcS2z

[techmannih]

please remove console.log

[seveibar]

where is the evidence this works?

[natinew77-creator]

Evidence: Decoupling Capacitor Linear Layout

Thanks for the feedback! I've addressed the review comments:

Changes Made

1. Removed all console.log statements from tests
2. Added proper assertions to verify linear arrangement (expect(ys.size).toBe(1))

Visual Evidence

Here's a screenshot from the Cosmos debugger showing the decoupling capacitor packing in action:

What the visualization shows:

• Main Chip (U3): Large cyan/teal component on the right with multiple pins
• Decoupling Capacitors (C9, C18, C7): Arranged in a neat horizontal linear row to the left
• Net Connections: Grey lines showing the connectivity between chip pins and capacitors
• C10, C11: Additional capacitors shown in their own row

The capacitors are:

• Sorted by their connection to the main chip's pins
• Placed in a linear row with consistent spacing
• No overlapping or messy arrangements

Test Verification

The test now includes proper assertions:

// Verify linear arrangement (all same Y for horizontal row)
const ys = new Set(positions.map((p) => p.y.toFixed(3)))
expect(ys.size).toBe(1) // All capacitors should have same Y coordinate

All tests pass with 5 expect() calls verifying the layout.

[natinew77-creator]

Hi @seveibar and @techmannih, I've updated the PR with the requested visual evidence and addressed the feedback regarding console logs and test assertions.
The layout now consistently produces the neat, linear arrangement shown in the screenshot. Could you please take another look?

[seveibar]

needs visual snapshot testing (i.e. svgs, as is our standard practice)