GitHub - tumsifu1/simpleRISC-Computer: The objective of this project is to develop, simulate, implement, and validate a Mini SRC (simpleRISC Computer). This comprehensive project involves several key components:

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 98 Commits
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
ADD_ALUtb.v		ADD_ALUtb.v
ALU.v		ALU.v
ALU.v.bak		ALU.v.bak
AND_ALUtb.v		AND_ALUtb.v
AND_ALUtb.v.bak		AND_ALUtb.v.bak
CON_FF_LOGIC.v.bak		CON_FF_LOGIC.v.bak
Con_FF_logic.v		Con_FF_logic.v
DIV_ALUtb.v		DIV_ALUtb.v
DIV_ALUtb.v.bak		DIV_ALUtb.v.bak
ELEC374Project.done		ELEC374Project.done
ELEC374Project.fit.rpt		ELEC374Project.fit.rpt
ELEC374Project.fit.summary		ELEC374Project.fit.summary
ELEC374Project.flow.rpt		ELEC374Project.flow.rpt
ELEC374Project.map.rpt		ELEC374Project.map.rpt
ELEC374Project.map.smsg		ELEC374Project.map.smsg
ELEC374Project.map.summary		ELEC374Project.map.summary
ELEC374Project.qpf		ELEC374Project.qpf
ELEC374Project.qws		ELEC374Project.qws
ELEC374Project_description.txt		ELEC374Project_description.txt
ELEC374Project_nativelink_simulation.rpt		ELEC374Project_nativelink_simulation.rpt
ELEC374project.qsf		ELEC374project.qsf
MAR.v		MAR.v
MDR.v		MDR.v
MDR.v.bak		MDR.v.bak
MDRTB.v		MDRTB.v
MDRTB.v.bak		MDRTB.v.bak
MULTIPLY_ALUtb.v		MULTIPLY_ALUtb.v
MULTIPLY_ALUtb.v.bak		MULTIPLY_ALUtb.v.bak
MUL_ALUtb.v		MUL_ALUtb.v
NEGATE_ALUtb.v		NEGATE_ALUtb.v
NEGATE_ALUtb.v.bak		NEGATE_ALUtb.v.bak
NOT_ALUtb.v		NOT_ALUtb.v
NOT_ALUtb.v.bak		NOT_ALUtb.v.bak
OR_TBdatapath.v		OR_TBdatapath.v
PC.v		PC.v
PC.v.bak		PC.v.bak
R0_register.v		R0_register.v
Register.asm.rpt		Register.asm.rpt
Register.done		Register.done
Register.fit.rpt		Register.fit.rpt
Register.fit.smsg		Register.fit.smsg
Register.fit.summary		Register.fit.summary
Register.flow.rpt		Register.flow.rpt
Register.jdi		Register.jdi
Register.map.rpt		Register.map.rpt
Register.map.smsg		Register.map.smsg
Register.map.summary		Register.map.summary
Register.pin		Register.pin
Register.qsf		Register.qsf
Register.qws		Register.qws
Register.sof		Register.sof
Register.sta.rpt		Register.sta.rpt
Register.sta.summary		Register.sta.summary
Register.v		Register.v
Register_description.txt		Register_description.txt
Register_nativelink_simulation.rpt		Register_nativelink_simulation.rpt
SUB_ALUtb.v		SUB_ALUtb.v
add_32.v		add_32.v
add_32.v.bak		add_32.v.bak
add_TB.v		add_TB.v
add_TB.v.bak		add_TB.v.bak
and_32bit.v		and_32bit.v
and_TB.v.bak		and_TB.v.bak
bidirectional_bus.v		bidirectional_bus.v
bidirectional_bus.v.bak		bidirectional_bus.v.bak
datapath.v		datapath.v
datapath.v.bak		datapath.v.bak
decoder2_to_4.v		decoder2_to_4.v
decoder_4_to_16.sv		decoder_4_to_16.sv
div_32bit.v		div_32bit.v
div_32bit.v.bak		div_32bit.v.bak
div_32bit_tb.v		div_32bit_tb.v
div_32bit_tb.v.bak		div_32bit_tb.v.bak
div_tb.v.bak		div_tb.v.bak
encoder.v		encoder.v
encoder.v.bak		encoder.v.bak
encoderTB.v		encoderTB.v
encoderTB.v.bak		encoderTB.v.bak
encoder_32to5.v		encoder_32to5.v
encoder_32to5.v.bak		encoder_32to5.v.bak
memory_file.mif		memory_file.mif
mul_32bit.v		mul_32bit.v
mul_32bit.v.bak		mul_32bit.v.bak
mul_32bit_tb.v		mul_32bit_tb.v
mul_32bit_tb.v.bak		mul_32bit_tb.v.bak
mul_tb.v.bak		mul_tb.v.bak
multiplexer.v		multiplexer.v
multiplexer.v.bak		multiplexer.v.bak
multiplexer32to1.v		multiplexer32to1.v
multiplexer32to1.v.bak		multiplexer32to1.v.bak
multiplexerTB.v		multiplexerTB.v
mux2to1TB.v		mux2to1TB.v
mux2to1TB.v.bak		mux2to1TB.v.bak
negate.v		negate.v
negate.v.bak		negate.v.bak
not_32bit.v		not_32bit.v

About

The objective of this project is to develop, simulate, implement, and validate a Mini SRC (simpleRISC Computer). This comprehensive project involves several key components: