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Synchronize sim success between chiptops#2326

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schwarz-em wants to merge 2 commits intomainfrom
multi-sim-sync
Open

Synchronize sim success between chiptops#2326
schwarz-em wants to merge 2 commits intomainfrom
multi-sim-sync

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@schwarz-em schwarz-em commented Feb 24, 2026

Previously, in multi-chip simulations, the harness success signal was set by multiple drivers. This fix allows the simulation to run until all chiptops have asserted success by creating a success signal per chiptop. By default, success is the OR of all chiptop successes (equivalent to previous behavior), but the success function is parameterized so the user can specify their own success criteria.

Related PRs / Issues:

Type of change:

  • Bug fix
  • New feature
  • Other enhancement

Impact:

  • RTL change
  • Software change (RISC-V software)
  • Build system change
  • Other

Contributor Checklist:

  • Did you set main as the base branch?
  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
  • Did you state the type-of-change/impact?
  • Did you delete any extraneous prints/debugging code?
  • Did you mark the PR with a changelog: label?
  • (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
  • (If applicable) Did you add documentation for the feature?
  • (If applicable) Did you add a test demonstrating the PR?
  • (If applicable) Did you mark the PR as Please Backport?

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  • ci:fpga-deploy - Run FPGA-based E2E testing
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