Pinned Loading

1. Development-of-AXI4-Verification-IP-VIP-using-UVM Development-of-AXI4-Verification-IP-VIP-using-UVM Public

   Configurable AXI4 Verification IP developed using UVM, featuring reusable master and slave agents, protocol checking, functional coverage, and scoreboard-based verification.

   SystemVerilog 1

2. AHB_APB_Bridge_Verification AHB_APB_Bridge_Verification Public

   UVM-based verification of an AHB-to-APB bridge, validating protocol compliance, address decoding, data integrity, error handling, and corner cases using constrained-random testing and functional co…

   SystemVerilog

3. UART-RX-TX-Asynchronous-Serial-Communication-Core UART-RX-TX-Asynchronous-Serial-Communication-Core Public

   Verilog-based UART RX–TX core implementing asynchronous serial communication with baud-rate generation, FSM-based transmitter and receiver, and simulation-based validation.

   SystemVerilog

4. RISC-V-RV32I-Processor-Design-and-Verification RISC-V-RV32I-Processor-Design-and-Verification Public

   RISC-V processor core under development, focusing on RV32I RTL design and phased verification using SystemVerilog and UVM.

   Verilog 1