feat: Add CXXRTL-based simulation infrastructure

.github/workflows/coverage.yml

@@ -24,7 +24,7 @@ jobs:
           cache: true
 
       - name: Install dependencies with multirepo
-        uses: chipflow/pdm-multirepo@v3
+        uses: chipflow/pdm-multirepo@v4
 
       - name: Build coverage file
         run: |

.github/workflows/main.yaml

@@ -30,7 +30,7 @@ jobs:
           cache: true
 
       - name: Install dependencies with multirepo
-        uses: chipflow/pdm-multirepo@v3
+        uses: chipflow/pdm-multirepo@v4
 
       - name: Run tests
         run: pdm run test

.github/workflows/preview-docs.yml

@@ -20,7 +20,7 @@ jobs:
           cache: true
 
       - name: Install dependencies with multirepo
-        uses: chipflow/pdm-multirepo@v3
+        uses: chipflow/pdm-multirepo@v4
 
       - name: Build docs
         run: pdm docs

.github/workflows/test-examples.yml

@@ -85,7 +85,7 @@ jobs:
           cache-dependency-path: './**/pyproject.toml'
 
       - name: Install dependencies with multirepo
-        uses: chipflow/pdm-multirepo@v3
+        uses: chipflow/pdm-multirepo@v4
         with:
           working-directory: ${{ env.test_repo_path }}
 

.gitignore

@@ -21,3 +21,9 @@ docs/_build
 docs/autoapi
 docs/chipflow-lib
 .cache
+
+# Build artifacts
+/build/
+
+# Claude Code
+.claude/

chipflow/sim/__init__.py

@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: BSD-2-Clause
+"""CXXRTL-based simulation infrastructure for ChipFlow.
+
+This module provides Python bindings for CXXRTL simulation, enabling fast
+compiled simulation of mixed Amaranth/Verilog/SystemVerilog designs.
+
+Example usage::
+
+    from chipflow.sim import CxxrtlSimulator, build_cxxrtl
+
+    # Build CXXRTL shared library from sources
+    lib_path = build_cxxrtl(
+        sources=["design.v", "ip.sv"],
+        top_module="design",
+        output_dir=Path("build/sim")
+    )
+
+    # Create simulator and run testbench
+    sim = CxxrtlSimulator(lib_path, top_module="design")
+    sim.reset()
+
+    # Access signals
+    sim.set("clk", 1)
+    sim.step()
+    value = sim.get("data_out")
+"""
+
+from chipflow.sim.cxxrtl import CxxrtlSimulator
+from chipflow.sim.build import build_cxxrtl
+
+__all__ = ["CxxrtlSimulator", "build_cxxrtl"]