Implementation of a Cryptographic Coprocessor of the PRESENT Lightweight Block Cipher (supporting encryption and decryption, and both 80-bit and 128-bit keys) and some Hardware Trojans, using VHDL

Dataset of Hardware-Trojan (HT) based Covert Channels (HT-CCs) for the IEEE 802.11 (WiFi) standard.

Benchmarking framework for ISPD'23 contest and TCHES'25 paper.

A curated paper list and resources on LLM-driven chip design automation and hardware security: RTL/HDL generation, PPA optimization, verification, debugging, trojan/vulnerability analysis, and tool-in-the-loop EDA workflows.

This project is a modified verison of the OpenRISC 1200 open-source processor, designed to estimate the feasibility of using an On-Chip Software Obfuscator to reduce the controllability over software activated Hardware Trojans.

Includes the code for detecting and classifying hardware trojans in RISC-V cores via machine learning models.

Supporting material for our RL-based Trojan insertion work at CCS 2022.

Architecture informatique post-silicium fusionnant l'intelligence distribuée du mycélium, la frustration géométrique des verres de spin et les modèles de sécurité "zombie" inspirés de l'Ophiocordyceps pour créer des réseaux auto-cicatrisants et résilients

🍄 Explore Bio-Physical architectures that leverage nature-inspired systems to overcome limits in computing and enhance adaptive intelligence.

🛡️ Explore LLM-driven chip design automation and hardware security with curated insights on intelligent EDA and lifecycle security practices.